TMS320VC5421 datasheet(21/104 Pages) TI1

21 / 104 page

Introduction

December 1999 − Revised October 2008

SPRS098D

Table 2−3. Signal Descriptions (Continued)

PIN NAME

DESCRIPTION

TYPE†

GENERAL-PURPOSE I/O PINS

A_XF

B_XF

O/Z

External flag output (latched software-programmable output-only signal). Bit-addressable. A_XF and

B_XF are placed into the high-impedance state when OFF is low.

A_GPIO0

I/O/Z

A_ROMEN

General-purpose I/O pins. The secondary function of these pins. In XIO mode, the

ROM enable (ROMEN) pins are used to enable the applicable on-chip ROM after

A_GPIO0

B_GPIO0

I/O/Z

B_ROMEN

ROM enable (ROMEN) pins are used to enable the applicable on-chip ROM after

reset.

A_GPIO1

B_GPIO1

I/O/Z

General-purpose I/O pins (software-programmable I/O signal). Values can be latched (output) by writ-

ing into the GPIO register. The states of GPIO pins (inputs) can be read by reading the GPIO register.

The GPIO direction is also programmable by way of the DIRn field in the GPIO register.

A_GPIO2/BIO

B_GPIO2/BIO

I/O/Z

General-purpose I/O. These pins can be configured like GPIO0−GPIO1; however, as an input, the pins

operate as the traditional branch control bit (BIO). If application code does not perform BIO-conditional

instructions, these pins operate as general inputs.

PRIMARY

A_GPIO3 (A_TOUT)

B_GPIO3 (B_TOUT)

I/O/Z

IOSTRB

When the device is in HPI mode and HMODE = 0 (multiplexed), these pins act

according to the general-purpose I/O control register. TOUT bit must be set to “1”

to drive the timer output on the pin. IF TOUT = 0, then these pins are

B_GPIO3 (B_TOUT)

I/O/Z

to drive the timer output on the pin. IF TOUT = 0, then these pins are

general-purpose I/Os. In EMIF mode (XIO = 1), these signals are active during I/O

space accesses.

MEMORY CONTROL SIGNALS

Program space select signal. The PS signal is asserted during external program space accesses. This pin

is placed into the high-impedance state when OFF is low.

This pin is also multiplexed with the HPI, and functions as the HDS1 data strobe input signal in HPI mode.

Refer to the HPI section of this table for details on the secondary function of this pin.

PS‡§

DS‡§

O/Z

Data space select signal. The DS signal is asserted during external data space accesses. This pin is

placed into the high-impedance state when OFF is low.

This pin is also multiplexed with the HPI, and functions as the HDS2 data strobe input signal in HPI mode.

Refer to the HPI section of this table for details on the secondary function of this pin.

I/O space select signal. The IS signal is asserted during external I/O space accesses. This pin is placed

into the high-impedance state when OFF is low.

This pin is also multiplexed with the general-purpose I/O feature, and functions as the B_GPIO3 (B_TOUT)

input/output signal in HPI mode. Refer to the General-Purpose I/O section of this table for details on the

secondary function of this pin.

MSTRB‡§

O/Z

Program and data memory strobe (active in EMIF mode). This pin is placed into the high-impedance state

when OFF is low.

READY

Data-ready input signal. READY indicates that the external device is prepared for a bus transaction to be

completed. If the device is not ready (READY = 0), the processor waits one cycle and checks READY

again. The processor performs the READY detection if at least two software wait states are programmed.

This pin is also multiplexed with the HPI, and functions as the host-port data ready (output) in HPI mode.

Refer to the HPI section of this table for details on the secondary function of this pin.

† I = Input, O = Output, S = Supply, Z = High Impedance

‡ This pin has an internal pullup resistor.

§ These pins are Schmitt triggered inputs.

¶ This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .

# This pin is used by Texas Instruments for device testing and should be left unconnected.

|| This pin has an internal pulldown resistor.

kAlthough this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,

a buffer is recommended to ensure the VIL and VIH specifications are met.

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