TMS320VC5421 datasheet(11/104 Pages) TI1

11 / 104 page

Features

December 1999 − Revised October 2008

SPRS098D

TMS320VC5421 Features

D 200-MIPS Dual-Core DSP Consisting of Two

Independent Subsystems

D Each Core Has an Advanced Multibus

Architecture With Three Separate 16-Bit

Data Memory Buses and One Program Bus

D 40-Bit Arithmetic Logic Unit (ALU)

Including a 40-Bit Barrel-Shifter and Two

40-Bit Accumulators Per Core

D Each Core Has a 17-Bit × 17-Bit Parallel

Multiplier Coupled to a 40-Bit Adder for

Non-Pipelined Single-Cycle Multiply/

Accumulate (MAC) Operations

D Each Core Has a Compare, Select, and

Store Unit (CSSU) for the Add/Compare

Selection of the Viterbi Operator

D Each Core Has an Exponent Encoder to

Compute an Exponent Value of a 40-Bit

Accumulator Value in a Single Cycle

D Each Core Has Two Address Generators

With Eight Auxiliary Registers and Two

Auxiliary Register Arithmetic Units

(ARAUs)

D 16-Bit Data Bus With Data Bus Holder

Feature

D 512K-Word × 16-Bit Extended Program

Address Space

D Total of 256K-Word × 16-Bit Dual- and

Single-Access On-Chip RAM (128K-Word x

16-Bit Two-Way Shared Memory)

D Single-Instruction Repeat and

Block-Repeat Operations

D Instructions With 32-Bit-Long Word

Operands

D Instructions With Two or Three Operand

Reads

D Fast Return From Interrupts

D Arithmetic Instructions With Parallel Store

and Parallel Load

D Conditional Store Instructions

D Output Control of CLKOUT

D Output Control of TOUT

D Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions

D Dual 1.8-V (Core) and 3.3-V (I/O) Power

Supplies for Low-Power, Fast Operations

D 10-ns Single-Cycle Fixed-Point Instruction

D Interprocessor Communication via Two

Internal 8-Element FIFOs

D Twelve Channels of Direct Memory Access

(DMA) for Data Transfers With No CPU

Loading (Six Channels Per Subsystem With

External Access)

D Six Multichannel Buffered Serial Ports

(McBSPs) With 128-Channel Selection

Capability (Three McBSPs per Subsystem)

D 16-Bit Host-Port Interface (HPI) Multiplexed

With External Memory Interface Pins

D Software-Programmable Phase-Locked

Loop (APLL) Provides Several Clocking

Options (Requires External Oscillator)

D On-Chip Scan-Based Emulation Logic,

IEEE Standard 1149-1{ (JTAG) Boundary-

Scan Logic

D Two Software-Programmable Timers

(One Per Subsystem)

D Software-Programmable Wait-State

Generator (14 Wait States Maximum)

D Provided in 144-pin MicroStar BGAt Ball

Grid Array (GGU Suffix) and 144-pin

Low-Profile Quad Flatpack (LQFP) (PGE

Suffix) Packages

‡ IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

MicroStar BGA is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

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