TMS320VC5421 datasheet(32/104 Pages) TI1

32 / 104 page

Functional Overview

December 1999 − Revised October 2008

SPRS098D

3.5.1 Software-Programmable Wait-State Generators

The software-programmable wait-state generator can be used to extend external bus cycles up to fourteen

machine cycles to interface with slower off-chip memory and I/O devices. The software wait-state register

(SWWSR) controls the operation of the wait-state generator. The SWWSR of a particular DSP subsystem

(A or B) is used for the external memory interface, depending on the state of the xDMA/XIO arbitration logic

(see Direct Memory Access (DMA) Controller section 3.8 and Table 3−4. The 14 least significant bits (LSBs)

of the SWWSR specify the number of wait states (0–7) to be inserted for external memory accesses to five

separate address ranges. This allows a different number of wait states for each of the five address ranges.

Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)

defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is

initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown

in Figure 3−3 and described in Table 3−4.

XPA

I/O

Data

Program

R/W=0

R/W=111

LEGEND: R = Read, W = Write

Figure 3−3. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

Table 3−4. Software Wait-State Register (SWWSR) Bit Fields

BIT

RESET

FUNCTION

NO.

NAME

RESET

VALUE

FUNCTION

XPA

Extended program address control bit. XPA is used in conjunction with the program space fields

(bits 0 through 5) to select the address range for program space wait states.

14−12

I/O

I/O space. The field value (0−7) corresponds to the base number of wait states for I/O space accesses

within addresses 0000−FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for

the base number of wait states.

11−9

Data

Upper data space. The field value (0−7) corresponds to the base number of wait states for external data

space accesses within addresses 8000−FFFFh. The SWSM bit of the SWCR defines a multiplication

factor of 1 or 2 for the base number of wait states.

8−6

Data

Lower data space. The field value (0−7) corresponds to the base number of wait states for external data

space accesses within addresses 0000−7FFFh. The SWSM bit of the SWCR defines a multiplication

factor of 1 or 2 for the base number of wait states.

5−3

Program

Upper program space. The field value (0−7) corresponds to the base number of wait states for external

program space accesses within the following addresses:

- XPA = 0: x8000−xFFFFh

- XPA = 1: The upper program space bit field has no effect on wait states.

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

2−0

Program

Program space. The field value (0−7) corresponds to the base number of wait states for external program

space accesses within the following addresses:

- XPA = 0: x0000−x7FFFh

- XPA = 1: 00000−3FFFFh

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

TMS320VC5421 датащи(PDF) 32 Page - Texas Instruments

TMS320VC5421 датащи(HTML) 32 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL