TMS320VC5421 datasheet(47/104 Pages) TI1

47 / 104 page

Functional Overview

December 1999 − Revised October 2008

SPRS098D

3.8.5 DMA in Autoinitialization Mode

The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers

can be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA,

DMGCR, and DMGFR). Autoinitialization allows:

•

Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the

completion of the current block transfers, but with the global reload registers, it can reinitialize these values

for the next block transfer any time after the current block transfer begins.

•

Repetitive operation: The CPU does not preload the global reload register with new values for each block

transfer but only loads them on the first block transfer.

The 5421 DMA has been enhanced to expand the DMA global reload register sets. Each DMA channel now

has its own DMA global reload register set. For example, the DMA global reload register set for channel 0 has

DMGSA0, DMGDA0, DMGCR0, and DMGFR0 while DMA channel 1 has DMGSA1, DMGDA1, DMGCR1,

and DMGFR1, etc.

To utilize the additional DMA global reload registers, the AUTOIX bit is added to the DMPREC register as

shown in Figure 3−17.

76543

210

FREE

AUTOIX

DPRC[5:0]

IOSEL

DE[5:0]

Figure 3−17. DMPREC Register

Table 3−12. DMA Global Reload Register Selection

AUTOIX

DMA GLOBAL RELOAD REGISTER USAGE IN AUTO INIT MODE

0 (default)

All DMA channels use DMGSA0, DMGDA0, DMGCR0 and DMGFR0

Each DMA channel uses its own set of global reload registers

3.8.6 Subsystem Communications

The 5421 device provides two options for efficient core-to-core communications:

•

Core-to-core FIFO communications

•

DMA global memory transfer

3.8.6.1

FIFO Data Communications

The subsystems’ FIFO communications interface is shown in the 5421 functional block diagram (Figure 3−1).

Two unidirectional 8-word-deep FIFOs are available in the device for efficient interprocessor communication:

one configured for core A-to-core B data transfers, and the other configured for core B-to-core A data transfers.

Each subsystem, by way of DMA control, can write to its respective output data FIFO and read from its

respective input data FIFO. The FIFOs are accessed using the DMAs I/O space, which is completely

independent of the CPU I/O space. The DMA transfers to or from the FIFOs can be synchronized to “receive

FIFO not empty” and “transmit FIFO not full” events, providing protection from overflow and underflow.

Subsystems can interrupt each other to flag when the FIFOs are either full or empty. The interprocessor

interrupt request bit (IPIRQ) (bit 8 in the BSCR register (BSCR.8)) is set to 1 to generate a PINT in the other

subsystem’s IFR.14. See the Interrupts section (Section 3.13) for more information.

3.8.6.2

DMA Global Memory Transfers

The 5421 enables each subsystem to transfer data directly between the memories that are CPU local via DMA

global memory transfers. The DMA global memory map is shown in Figure 3−13.

TMS320VC5421 датащи(PDF) 47 Page - Texas Instruments

TMS320VC5421 датащи(HTML) 47 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL