PC97338VLJ datasheet(159/221 Pages) NSC

159 / 221 page

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BSR – Bank Select Register

When bit 7 is 1, bits 0–6 of BSR are used to select the

bank. The encodings are shown in Table 80.

TABLE 80. Bank Selection Encoding

5.14.5 MCR – Modem/Mode Control

Used to control the interface with the modem or data

set, as well as the module operational mode. The

function of this register changes depending upon

whether the module is in extended or non-extended

mode. In extended mode the interrupt output signal is

always enabled and loopback can be selected by set-

ting bit 4 of the EXCR1 register. Upon reset, all bits

are set to 0.

Non-Extended Mode

The format of the non-extended mode MCR is shown

in Figure 88.

FIGURE 88. Modem Control Register,

Non-Extended Mode

Extended Mode

The format of the extended mode MCR is shown in

Figure 88.

Note: Bits 2 to 7 should always be initialized after the

operational mode is changed from non-extended to

extended.

FIGURE 88. Modem Control Register,

Extended Modes

BSR Bits

Bank

Selected

76543

210

xxxx

xxx

xx1

xxx

11100

000

11100

100

11101

000

11101

100

11110

000

11110

100

11111x

Reserved

321

Reset

Required

RILP

LOOP

Reserved

DTR

RTS

ISEN / DCDLP

DTR – Data Terminal Ready.

This bit controls the DTR signal output.

When it is set to 1, DTR is driven low.

In loopback mode this bit internally drives

DSR.

RTS – Request to Send.

This bit controls the RTS signal output.

When it is set to 1, RTS is driven low.

In loopback mode this bit internally drives CTS.

RILP – Loopback RI.

In normal operation this bit is unused.

In loopback mode this bit internally drives RI.

ISEN/DCDL – Interrupt Signal Enable/Loop-

back DCD.

In normal operation this bit controls the inter-

rupt signal, and it must be set to 1 in order to

enable it.

In loopback mode, this bit internally drives

DCD, and the interrupt signal is always en-

abled.

Note: New programs should always keep this

bit set to 1 during normal operation. The inter-

rupt signal should be controlled through the

Plug-n-Play logic.

LOOP – Loopback Enable.

When set to 1, loopback mode is selected.

This bit accesses the same internal register as

bit 4 of the EXCR1 register.

Refer to the section describing the EXCR1 reg-

ister for more information on the loopback

mode.

B7–5 Reserved.

Forced to 0.

321

Reset

Required

DMA_EN

IR_PLS

MDSL0

MDSL1

MDSL2

DTR

RTS

TX_DFR

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