PC97307 datasheet(146/218 Pages) NSC

146 / 218 page

146

UART1 and UART2 (with IR) (Logical Devices 5 and 6)

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Link Control Register (LCR), All Banks, Offset 03h

Bits 6-0 are only effective in UART, Sharp-IR and SIR

modes. They are ignored in Consumer-IR mode.

FIGURE 7-11. LCR Register Bitmap

Bits 1,0 - Character Length Select (WLS1,0)

These bits specify the number of data bits in each trans-

mitted or received serial character. Table 7-7 shows

how to encode these bits.

TABLE 7-7. Word Length Select Encoding

Bits 2 - Number of Stop Bits (STB)

This bit specifies the number of stop bits transmitted

with each serial character.

0 - One stop bit is generated. (Default)

1 - If the data length is set to 5-bits via bits 1,0

(WLS1,0), 1.5 stop bits are generated. For 6, 7 or 8

bit word lengths, two stop bits are transmitted. The

receiver checks for one stop bit only, regardless of

the number of stop bits selected.

Bit 3 - Parity Enable (PEN)

This bit enable the parity bit See Table 7-8 on page 146.

The parity enable bit is used to produce an even or odd

number of 1s when the data bits and parity bit are

summed, as an error detection device.

0 - No parity bit is used. (Default)

1 - A parity bit is generated by the transmitter and

checked by the receiver.

Bit 4 - Even Parity Select (EPS)

When Parity is enabled (PEN is 1), this bit, together with

bit 5 (STKP), controls the parity bit as shown in Table

7-8.

0 - If parity is enabled, an odd number of logic 1s are

transmitted or checked in the data word bits and

parity bit. (Default)

WLS1

WLS0

Character Length

5 (Default)

76543210

Reset

Required

Link Control

All Banks,

Offset 03h

STB

EPS

STKP

SBRK

BKSE

WLS0

WLS1

PEN

1 - If parity is enabled, an even number of logic 1s are

transmitted or checked.

Bit 5 - Stick Parity (STKP)

When Parity is enabled (PEN is 1), this bit, together with

bit 4 (EPS), controls the parity bit as show in Table 7-8.

TABLE 7-8. Bit Settings for Parity Control

Bit 6 - Set Break (SBRK)

This bit enables or disables a break. During the break,

the transmitter can be used as a character timer to ac-

curately establish the break duration.

This bit acts only on the transmitter front-end and has no

effect on the rest of the transmitter logic.

When set to 1 the following occurs:

— If a UART mode is selected, the SOUT pin is forced

to a logic 0 state.

— If SIR mode is selected, pulses are issued continu-

ously on the IRTX pin.

— If Sharp-IR mode is selected and internal modula-

tion is enabled, pulses are issued continuously on

the IRTX pin.

— If Sharp-IR mode is selected and internal modula-

tion is disabled, the IRTX pin is forced to a logic 1

state.

To avoid transmission of erroneous characters as a re-

sult of the break, use the following procedure to set

SBRK:

1. Wait for the transmitter to be empty. (TXEMP = 1).

2. Set SBRK to 1.

3. Wait for the transmitter to be empty, and clear SBRK

when normal transmission must be restored.

Bit 7 - Bank Select Enable (BKSE)

0 - This register functions as the Link Control Register

(LCR).

1 - This register functions as the Bank Select Register

(BSR).

PEN

EPS

STKP

Selected Parity Bit

None

Odd

Even

Logic 1

Logic 0

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