PC97307 datasheet(81/218 Pages) NSC

81 / 218 page

The Digital Floppy Disk Controller (FDC) (Logical Device 3)

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The controller also uses the drive polling phase to automat-

ically trigger power down. When the specified time that the

motor may be off expires, the controller waits 512 msec,

based on data transfer rates of 500 Kbps and 1 Mbps, be-

fore powering down, if this function is enabled via the

MODE command.

If a new command is issued while the FDC is in the drive

polling phase, the MSR does not indicate a ready status for

the next parameter byte until the polling sequence com-

pletes the loop. This can cause a delay between the first

and second bytes of up to 500

µsec at 250 Kbps.

5.5

THE RESULT PHASE STATUS REGISTERS

In the result phase of a command, result bytes that hold sta-

tus information are read from the Data Register (FIFO) at

offset 05h. These bytes are the result phase status regis-

ters.

The result phase status registers may only be read from the

Data Register (FIFO) during the result phase of certain

commands, unlike the Main Status Register (MSR), which

is a read only register that is always valid.

5.5.1

Result Phase Status Register 0 (ST0)

FIGURE 5-16. ST0 Result Phase Register Bitmap

Bits 1,0 - Logical Drive Selected

These two binary encoded bits indicate the logical drive

selected at the end of the execution phase.

The value of these bits is reflected in bits 1,0 of the SR3

00 - Drive 0 selected.

01 - Drive 1 selected.

10 - If four drives are supported, or drives 2 and 0 are

exchanged, drive 2 is selected.

11 - If four drives are supported, drive 3 is selected.

Bit 2 - Head Selected

This bit indicates which side of the Floppy Disk Drive

(FDD) is selected. It reflects the status of the HDSEL

signal at the end of the execution phase.

The value of this bit is reflected in bit 2 of the ST3 regis-

ter, described on page 83.

0 - Side 0 is selected.

1 - Side 1 is selected.

Bit 3 - Not used.

This bit is not used and is always 0.

76543210

Reset

Required

Result Phase Status

Head Selected (Execution Phase)

SEEK End

Interrupt Code

Not Used

Equipment Check

Logical Drive Selected

(Execution Phase)

Bit 4 - Equipment Check

After a RECALIBRATE command, this bit indicates

whether the head of the selected drive was at track 0,

i.e., whether or not TRK0 was active. This information is

used during the SENSE INTERRUPT command.

0 - Head was at track 0, i.e., a TRK0 pulse occurred af-

ter a RECALIBRATE command.

1 - Head was not at track 0, i.e., no TRK0 pulse oc-

curred after a RECALIBRATE command.

Bit 5 - SEEK End

This bit indicates whether or not a SEEK, RELATIVE

SEEK, or RECALIBRATE command was completed by

the controller. Used during a SENSE INTERRUPT com-

mand.

0 - SEEK, RELATIVE SEEK, or RECALIBRATE com-

mand not completed by the controller.

1 - SEEK, RELATIVE SEEK, or RECALIBRATE com-

mand was completed by the controller.

Bits 7,6 - Interrupt Code (IC)

These bits indicate the reason for an interrupt.

00 - Normal termination of command.

01 - Abnormal termination of command. Execution of

command was started, but was not successfully

completed.

10 - Invalid command issued. Command issued was

not recognized as a valid command.

11 - Internal drive ready status changed state during

the drive polling mode. This only occurs after a

hardware or software reset.

5.5.2

Result Phase Status Register 1 (ST1)

FIGURE 5-17. ST1 Result Phase Register Bitmap

Bit 0 - Missing Address Mark

This bit indicates whether or not the Floppy Disk Con-

troller (FDC) failed to find an address mark in a data field

during a read, scan, or verify command.

0 - No missing address mark.

1 - Address mark missing.

Bit 0 of the result phase Status register 2 (ST2) in-

dicates the when and where the failure occurred.

See Section 5.5.3 on page 82.

76543210

Reset

Required

Result Phase Status

Missing Data

CRC Error

End of Track

Not Used

Overrun or Underrun

Missing Address Mark

Not Used

Drive Write Protected

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