PC97307 datasheet(150/218 Pages) NSC

150 / 218 page

150

UART1 and UART2 (with IR) (Logical Devices 5 and 6)

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FIGURE 7-16. MSR Register Bitmap

Bit 0 - Delta Clear to Send (DCTS)

Set to 1, when the CTS input signal changes state.

This bit is cleared upon read.

Bit 1 - Delta Data Set Ready (DDSR)

Set to 1, when the DSR input signal changes state.

This bit is cleared upon read

Bit 2 - Trailing Edge Ring Indicate (TERI)

Set to 1, when the RI input signal changes state from

low to high.

This bit is cleared upon read

Bit 3 - Delta Data Carrier Detect (DDCD)

Set to 1, when the DCD input signal changes state.

1 - DCD signal state changed.

Bit 4 - Clear To Send (CTS)

This bit returns the inverse of the CTS input signal.

Bit 5 - Data Set Ready (DSR)

This bit returns the inverse of the DSR input signal.

Bit 6 - Ring Indicate (RI)

This bit returns the inverse of the RI input signal.

Bit 7 - Data Carrier Detect (DCD)

This bit returns the inverse of the DCD input signal.

76543210

Reset

Required

Modem Status

Bank 0,

TERI

CTS

DSR

DCD

DCTS

DDSR

DDCD

Offset 06h

7.11.10 Scratchpad Register (SPR), Bank 0, Offset 07h

This register shares a common address with the ASCR Register.

In Non-Extended mode, this is a scratch register (as in the

16550) for temporary data storage.

FIGURE 7-17. SPR Register Bitmap

7.11.11 Auxiliary Status and Control Register (ASCR),

Bank 0, Offset 07h

This register shares a common address with the previous

one (SCR).

This register is accessed when the Extended mode of op-

eration is selected. The definition of the bits in this case is

dependent upon the mode selected in the MCR register,

bits 7 through 5. This register is cleared upon hardware re-

set or when the operational mode changes. Bits 2 and 6 are

cleared when the transmitter is “soft reset”. Bits 0,1,4 and 5

are cleared when the receiver is “soft reset”.

FIGURE 7-18. ASCR Register Bitmap

Bit 0 - RX_FIFO Time-Out (RXF_TOUT)

This bit is read only and set to 1 when an RX_FIFO tim-

eout occurs. It is cleared when a character is read from

the RX_FIFO.

Bit 1 -Reserved

Read/Write 0.

76543210

Reset

Required

Scratchpad Register

(SCR)

Bank 0,

Scratch Data

Non-Extended Modes

Offset 07h

76543210

Reset

Required

Auxiliary Status

Bank 0,

Reserved

RXACT

TXUR

Reserved

S_EOT

RXWDG

RXF_TOUT

Extended Modes

Reserved

Offset 07h

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