PC97307 datasheet(62/218 Pages) NSC

62 / 218 page

Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)

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4.5.4

RAM Lock Register (RLR), Index 47h

Once a non-reserved bit is set to 1 it can be cleared only by

hardware (MR pin) reset.

FIGURE 4-14. RAM Lock Register

Bit 2-0 - Reserved

Reserved.

Bit 3 - Upper RAM Block

Controls access to the upper 128 RAM bytes, accessed

via the Upper RAM Address and Data Ports of bank 1

0 - This bit has no effect on upper RAM access.

1 - Upper RAM Data Port of bank 1 is blocked: writes

are ignored and reads return FFh.

Bit 4 - RAM Block Read

This bit controls reads from RAM bytes 80h-9Fh (00h-

1Fh of upper RAM).

0 - This bit has no effect on upper RAM access.

1 - Reads from bytes 00h-1Fh of upper RAM return

FFh.

Bit 5 - RAM Block Write

This bit controls writes to bytes 80h-9Fh (00h-1Fh of up-

per RAM).

0 - This bit has no effect on upper RAM access.

1 - Writes to bytes 00h-1Fh of upper RAM are ignored.

Bit 6 - RAM Mask Write

This bit controls writes to all RTC RAM.

0 - This bit has no effect on RAM access.

1 - Writes to bank 0 RAM and to upper RAM are ig-

nored.

Bit 7 - RAM Lock

0 - This bit has no effect on RAM access.

1 - Read and write to locations 38h-3Fh of all banks

are blocked. Writes are ignored, and reads return

FFh.

Reserved

RAM Block Read

RAM Block Write

RAM Mask Write

RAM Lock

76543210

Reserved

Upper RAM Block

Index 47h

Power-Up

Required

RAM Lock

(RLR)

Reset

4.6

RTC AND APC REGISTER BITMAPS

4.6.1

RTC Register Bitmaps

RS2

DV0

DV2

UIP

76543210

RS0

RS3

DV1

RS1

UIE

AIE

PIE

SET

76543210

DSE

24 or 12 Hour Mode

Unused

IRQF

76543210

Reserved

Index 0Ah

Power-Up

Required

RTC Control

(CRA)

Reset

Index 0Bh

Power-Up

Required

RTC Control

(CRB)

Reset

Index 0Ch

Power-Up

Required

RTC Control

(CRC)

Reset

VRT

76543210

Reserved

Index 0Dh

Power-Up

Required

RTC Control

(CRD)

Reset

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