PC97307 datasheet(147/218 Pages) NSC

147 / 218 page

147

UART1 and UART2 (with IR) (Logical Devices 5 and 6)

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7.11.6

Bank Selection Register (BSR), All Banks,

Offset 03h

FIGURE 7-12. BSR Register Bitmap

The Bank Selection Register (BSR) selects which register

bank is to be accessed next.

About accessing this register see the description of bit 7 of

the LCR Register.

Bits 6-0 - Bank Selection

When bit 7 is set to 1, bits 6-0 of BSR select the bank,

as shown in Table 7-9.

Bit 7 - Bank Selection Enable (BKSE)

0 - Bank 0 is selected.

1 - Bits 6-0 specify the selected bank.

TABLE 7-9. Bank Selection Encoding

BSR Bits

Bank

Selected

LCR

76543210

LCR is writ-

ten

xxxxxx

xxxx

xxxxx

LCR is not

written

11100100

11101000

11101100

11110000

11110100

Reserved

76543210

Reset

Required

Bank Selection

All Banks,

Offset 03h

Bank Selection

BKSE-Bank Selection Enable

7.11.7

Modem/Mode Control Register (MCR), Bank 0,

Offset 04h

This register controls the interface with the modem or data

communications set, and the device operational mode

when the device is in the Extended mode. The register

function differs for Extended and Non-Extended modes.

Modem/Mode Control Register (MCR), Non-Extended

Mode, Bank 0, Offset 04h

FIGURE 7-13. MCR Register Bitmap, Non-Extended

Mode

Bit 0 - Data Terminal Ready (DTR)

This bit controls the DTR signal output. When set to 1,

DTR is driven low. When loopback is enabled (LOOP is

set to 1), this bit internally drives DSR.

Bit 1 - Request To Send (RTS)

This bit controls the RTS signal output. When set to 1,

drives RTS low. When loopback is enabled (LOOP is

set), this bit drives CTS, internally.

Bit 2 - Loopback Interrupt Request (RILP)

When loopback is enabled, this bit internally drives RI.

Otherwise it is unused.

Bit 3 - Interrupt Signal Enable (ISEN) or Loopback DCD

(DCDLP)

In normal operation (standard 16450 or 16550) mode,

this bit controls the interrupt signal and must be set to 1

in order to enable the interrupt request signal.

When loopback is enabled, the interrupt output signal is

always enabled, and this bit internally drives DCD.

New programs should always keep this bit set to 1 dur-

ing normal operation. The interrupt signal should be

controlled through the Plug-n-Play logic.

Bit 4 - Loopback Enable (LOOP)

When this bit is set to 1, it enables loopback. This bit ac-

cesses the same internal register as bit 4 of the EXCR1

154 for more information on the Loopback mode).

0 - Loopback disabled. (Default)

1 - Loopback enabled.

Bits 7-5 - Reserved

Read/Write 0.

76543210

Reset

Required

Modem Control

Bank 0,

Non-Extended UART mode

RILP

LOOP

Reserved

DTR

RTS

ISEN or DCDLP

Offset 04h

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