PC97307 datasheet(38/218 Pages) NSC

38 / 218 page

Configuration

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This option supports run-time conﬁguration within

the Parallel Port address space. An 8-byte (and

1024-byte) aligned base address is required to ac-

cess these registers. See Chapter 6 on page 111

for details.

Bit 7-5 - Parallel Port Mode Select

Bit 5 is the LSB.

Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled

by bit 4 of the Control2 configuration register of the par-

allel port at offset 02h. See Section 6.5.17 on page 126.

000 - SPP Compatible mode. PD7-0 are always output

signals.

001 - SPP Extended mode. PD7-0 direction controlled

by software.

010 - EPP 1.7 mode.

011 - EPP 1.9 mode.

100 - IEEE1284 mode (IEEE1284 register set), with no

support for EPP mode.

101 - Reserved.

110 - Reserved.

111 - IEEE1284 mode (IEEE1284 register set), with

EPP mode selectable as mode 4.

2.8

UART2 AND INFRARED CONFIGURATION

2.8.1

SuperI/O UART2 Configuration Register,

Index F0h

This read/write register is reset by hardware to 02h.

FIGURE 2-12. SuperI/O UART2 Conﬁguration Register

Bitmap

Bit 0 - TRI-STATE Control for UART signals

This bit controls the TRI-STATE status of UART signals

(except IRQ and DMA signals) when the UART is inac-

tive (disabled). This bit is ORed with a bit of the PMC1

vice 8).

0 - Signals not in TRI-STATE.

1 - Signals in TRI-STATE.

Bit 1 - Power Mode Control

0 - Low power mode.

TRI-STATE Control for

Bank Select Enable

76543210

Reset

Required

Index F0h

Configuration Register,

Ring Detection on RI Pin

SuperI/O UART2

Power Mode Control

Busy Indicator

Reserved

UART2 Signals

UART Clock disabled. UART output signals are set

to their default state. The RI input signal can be

programmed to generate an interrupt. Registers

are maintained.

1 - Normal power mode.

UART clock enabled. The UART is functional when

the logical device is active. This bit is ANDed with a

bit of the PMC3 register of the power management

device (logical device 8)

Bit 2 - Busy Indicator

This read-only bit can be used by power management

software to decide when to power down the logical de-

vice. This bit is also accessed via the PMC3 register of

the power management device (logical device 8).

0 - No transfer in progress.

1 - Transfer in progress.

Bit 3 - Ring Detection on RI Pin

0 - The UART RI input signal uses the RI pin.

1 - The UART RI input signal is the RING detection

signal on the RING pin. RING pin is selected by the

APCR2 register of the Advanced Power Control

(APC) module.

Bits 6-4 - Reserved

These bits are reserved.

Bit 7 - Bank Select Enable

Enables bank switching. If this bit is cleared, all attempts

to access the extended registers are ignored.

2.9

UART1 CONFIGURATION REGISTER

(LOGICAL DEVICE 6)

2.9.1

SuperI/O UART1 Configuration Register,

Index F0h

This read/write register is reset by hardware to 02h. Its bits

function like the bits in the SuperI/O UART2 Configuration

FIGURE 2-13. SuperI/O UART1 Conﬁguration Register

Bitmap

TRI-STATE Control for

Bank Select Enable

76543210

Reset

Required

Index F0h

Configuration Register,

Ring Detection on RI Pin

SuperI/O UART1

Power Mode Control

Busy Indicator

Reserved

UART1 Pins

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