PC97307 datasheet(26/218 Pages) NSC

26 / 218 page

Configuration

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TABLE 2-4. Parallel Port Address Range Allocation

a. The SuperI/O processor does not decode the Parallel Port outside this range.

Parallel Port Mode

SuperI/O Parallel Port

Conﬁguration Register Bits

Decoded Range a

SPP

Three registers, from base to base + 02h

EPP (Non ECP Mode 4)

Eight registers, from base to base + 07h

ECP, No Mode 4,

No Internal Conﬁguration

Six registers, from base to base + 02h and

from base + 400h to base + 402h

ECP with Mode 4,

No Internal Conﬁguration

11 registers, from base to base + 07h and

from base + 400h to base + 402h

ECP with Mode 4,

Conﬁguration within Parallel Port

16 registers, from base to base + 07h and

from base + 400h to base + 407h

2.3

THE CONFIGURATION REGISTERS

The configuration registers control the setup of the part.

Their major functions are to:

• Identify the chip

• Enable major functions (such as, the Keyboard Control-

ler (KBC) for the keyboard and the mouse, the Real-

Time Clock (RTC), including Advanced Power Control

(APC), the Floppy Disc Controller (FDC), UARTs, paral-

lel and general purpose ports, power management and

pin functionality)

• Define the I/O addresses of these functions

• Define the status of these functions upon reset

Section 2.3.2 summarizes information for each register of

each function. In addition, the following non-standard, or

card control registers are described in detail in Section 2.4,

starting on page 34.

• Card Control Registers

— SuperI/O Conﬁguration 1 Register (SIOC1)

— SuperI/O Conﬁguration 2 Register (SIOC2)

— Programmable Chip Select Conﬁguration Index

— Programmable Chip Select Conﬁguration Data Reg-

ister

• KBC Configuration Register (Logical Device 0)

— SuperI/O KBC Conﬁguration Register

• FDC Configuration Registers (Logical Device 3)

— SuperI/O FDC Conﬁguration Register

— Drive ID Register

• Parallel Port Conﬁguration Register (Logical Device 4)

— SuperI/O Parallel Port Conﬁguration Register

• UART2 and Infrared Conﬁguration Register (Logical

Device 5)

— SuperI/O UART2 Conﬁguration Register

• UART1 Conﬁguration Register (Logical Device 6)

— SuperI/O UART1 Conﬁguration Register

• Programmable Chip Select Conﬁguration Registers

— CS0 Base Address MSB Register

— CS0 Base Address LSB Register

— CS0 Conﬁguration Register

— CS1 Base Address MSB Register

— CS1 Base Address LSB Register

— CS1 Conﬁguration Register

— CS2 Base Address MSB Register

— CS2 Base Address LSB Register

— CS2 Conﬁguration Register

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