PC97307 datasheet(78/218 Pages) NSC

78 / 218 page

The Digital Floppy Disk Controller (FDC) (Logical Device 3)

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5.3.9

Configuration Control Register (CCR),

Offset 07h, Write Operations

This write-only register can be used to set the data transfer

rate (in place of the DSR) for PC-AT, PS/2 and MicroChan-

nel applications. Other applications can set the data trans-

fer rate in the DSR. See Section 5.3.6.

This register is not affected by a software reset.

The data rate of the floppy controller is determined by the

last write to either the CCR register or to the DSR register.

FIGURE 5-15. CCR Register Bitmap

Bits 1,0 - Data Transfer Rate Select 1,0 (DRATE 1,0)

These bits determine the data transfer rate for the Flop-

py Disk Controller (FDC), depending on the supported

speeds.

Table 5-6 shows the data transfer rate selected by each

value of this field.

These bits are unaffected by a software reset, and are

set to 10 (250 Kbps) after a hardware reset.

Bits 7-2 - Reserved

These bits are reserved and should be set to 0.

5.4

THE PHASES OF FDC COMMANDS

FDC commands may be in the command phase, the execu-

tion phase or the result phase. The active phase determines

how data is transferred between the Floppy Disk Controller

(FDC) and the host microprocessor. When no command is

in progress, the FDC may be either idle or polling a drive.

5.4.1

Command Phase

During the command phase, the microprocessor writes a

series of bytes to the Data Register (FIFO). The first com-

mand byte contains the opcode for the command, which the

controller can interpret to determine how many more com-

mand bytes to expect. The remaining command bytes con-

tain the parameters required for the command.

The number of command bytes varies for each command.

All command bytes must be written in the order specified in

the Command Description Table in Section 5.7 on page 86.

The execution phase starts immediately after the last byte

in the command phase is written.

Prior to performing the command phase, the Digital Output

set with the Data rate Select Register (DSR) or the Config-

uration Control Register (CCR).

76543210

Reset

Required

Configuration Control

Offset 07h

Reserved

DRATE1

DRATE0

Write Operations

The Main Status Register (MSR) controls the flow of com-

mand bytes, and must be polled by the software before writ-

ing each command phase byte to the Data Register (FIFO).

Prior to writing a command byte, bit 7 of MSR (RQM, Re-

quest for Master) must be set and bit 6 of MSR (DIO, Data

I/O direction) must be cleared.

After the first command byte is written to the Data Register

(FIFO), bit 4 of MSR (CMD PROG, Command in Progress)

is also set and remains set until the last result phase byte is

read. If there is no result phase, the CMD PROG bit is

cleared after the last command byte is written.

A new command may be initiated after reading all the result

bytes from the previous command. If the next command re-

quires selection of a different drive or a change in the data

rate, the DOR and DSR or CCR should be updated, accord-

ingly. If the command is the last command, the software

should deselect the drive.

Normally, command processing by the controller core and

updating of the DOR, DSR, and CCR registers by the micro-

processor are operations that can occur independently of

one another. Software must ensure that the these registers

are not updated while the controller is processing a com-

mand.

5.4.2

Execution Phase

During the execution phase, the Floppy Disk Controller

(FDC) performs the desired command.

Commands that involve data transfers (e.g., read, write and

format operations) require the microprocessor to write or

read data to or from the Data Register (FIFO) at this time.

Some commands, such as SEEK or RECALIBRATE, con-

trol the read/write head movement on the disk drive during

the execution phase via the disk interface signals. Execu-

tion of other commands does not involve any action by the

microprocessor or disk drive, and consists of an internal op-

eration by the controller.

Data can be transferred between the microprocessor and

the controller during execution in DMA mode, interrupt

transfer mode or software polling mode. The last two modes

are non-DMA modes. All data transfer modes work with the

FIFO enabled or disabled.

DMA mode is used if the system has a DMA controller. This

allows the microprocessor to do other tasks while data

transfer takes place during the execution phase.

If a non-DMA mode is used, an interrupt is issued for each

byte transferred during the execution phase. Also, instead

of using the interrupt during a non-DMA mode transfer, the

Main Status Register (MSR) can be polled by software to in-

dicate when a byte transfer is required.

DMA Mode - FIFO Disabled

DMA mode is selected by writing a 0 to the DMA bit in the

SPECIFY command and by setting bit 3 of the DOR (DMA

enabled) to 1.

In the execution phase when the FIFO is disabled, each

time a byte is ready to be transferred, a DMA request (DRQ)

is generated in the execution phase. The DMA controller

should respond to the DRQ with a DMA acknowledge

(DACK) and a read or write pulse. The DRQ is cleared by

the leading edge of the active low DACK input signal. After

the last byte is transferred, an interrupt is generated, indi-

cating the beginning of the result phase.

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