PC97307 datasheet(148/218 Pages) NSC

148 / 218 page

148

UART1 and UART2 (with IR) (Logical Devices 5 and 6)

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Modem/Mode Control Register (MCR), Extended Mode,

Bank 0, Offset 04h

In Extended mode, this register is used to select the opera-

tion mode (IrDA, Sharp, etc.) of the device and to enable the

DMA interface. In these modes, the interrupt output signal

is always enabled, and loopback can be enabled by setting

bit 4 of the EXCR1 register.

FIGURE 7-14. MCR Register Bitmap, Extended Modes

Bit 0 - Data Terminal Ready (DTR)

This bit controls the DTR signal output. When set to1,

DTR is driven low. When loopback is enabled (LOOP is

set), this bit internally drives both DSR and RI.

Bit 1 - Request To Send (RTS)

This bit controls the RTS signal output. When set to1,

RTS is driven low. When loopback is enabled (LOOP is

set), this bit internally drives both CTS and DCD.

Bit 2 - DMA Enable (DMA_EN)

When set to1, DMA mode of operation is enabled. When

DMA is selected, transmit and/or receive interrupts

should be disabled to avoid spurious interrupts.

DMA cycles always address the Data Holding Registers

or FIFOs, regardless of the selected bank.

Bit 3 - Transmission Deferral (TX_DFR)

For a detailed description of the Transmission Deferral

see “Transmission Deferral” on page 139.

0 - No transmission deferral enabled. (Default)

1 - Transmission deferral enabled.

This bit is effective only if the Transmission FIFOs is en-

abled.

Bit 4 - Reserved

Read/Write 0.

Bits 7-5 - Mode Select (MDSL2-0)

These bits select the operational mode of the module

when in Extended mode, as shown in Table 7-10.

When the mode is changed, the transmission and re-

ception FIFOs are flushed, Link Status and Modem Sta-

tus Interrupts are cleared, and all of the bits in the

auxiliary status and control register are cleared.

76543210

Reset

Required

Modem Control

Bank 0,

Extended Mode

DMA_EN

Reserved

MDSL0

MDSL1

MDSL2

DTR

RTS

TX_DFR

Offset 04h

TABLE 7-10. The Module Operation Modes

7.11.8

Link Status Register (LSR), Bank 0, Offset 05h

This register provides status information concerning the

data transfer. Bits 1 through 4 indicate link status events.

These bits are sticky (they accumulate the occurrence of er-

ror conditions since the last time they were read). They are

cleared when one of the following events occurs:

• Hardware reset.

• The receiver is soft-reset.

• The LSR register is read.

Upon reset this register assumes the value of 0x60h.

The bit definitions change depending upon the operation

mode of the module.

Bits 4 through 1 of the LSR are the error conditions that gen-

erate a Receiver Link Status interrupt whenever any of the

corresponding conditions are detected and that interrupt is

enabled.

The LSR is intended for read operations only. Writing to the

LSR is not permitted

FIGURE 7-15. LSR Register Bitmap

Bit 0 - Receiver Data Available (RXDA)

Set to 1 when the Receiver Holding Register is full.

If the FIFOs are enabled, this bit is set when at least one

character is in the RX_FIFO.

Cleared when the CPU reads all the data in the Holding

MDSL2

(Bit 7)

MDSL1

(Bit 6)

MDSL0

(Bit 5)

Operational Mode

UART mode (Default)

Reserved

Sharp-IR

011

SIR

Reserved

Consumer-IR

Reserved

76543210

Reset

Required

Link Status

Bank 0,

BRK

TXRDY

TXEMP

ER_INF

RXDA

Offset 05h

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