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PC97307 датащи(PDF) 34 Page - National Semiconductor (TI) |
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PC97307 датащи(HTML) 34 Page - National Semiconductor (TI) |
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34 / 218 page ![]() 34 Configuration www.national.com TABLE 2-20. Power Management Configuration Registers - Logical Device 8 Index R/W Hard Reset Soft Reset Configuration Register or Action 30h R/W 00 00 Activate. When bit 0 is cleared, the registers of this logical device are not accessible. The registers are maintained. 31h R/W 00h 00h I/O Range Check. 60h R/W 00h 00h Base Address Most Significant Byte. 61h R/W 00h 00h Base Address LSB Register. Bit 0 (for A) is read only: 0. 74h R 04h 04h Report no DMA assignment. 75h R 04h 04h Report no DMA assignment. 2.4 CARD CONTROL REGISTERS This section describes the registers at first level indexes in the range 20h - 2Fh. 2.4.1 SID Register (In PC87307) This read-only register holds the revision and chip identity number of the chip. The PC87307VUL is identified by the value C0h in this register. FIGURE 2-1. SID Register Bitmap (In PC87307) 76543210 Reset Required 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 SID (In PC87307) Index 20h Register, Chip ID Revision ID 2.4.2 SID Register (In PC97307) This read-only register holds the identity number of the chip. The PC97307VUL is identified by the value CFh in this reg- ister. FIGURE 2-2. SID Register Bitmap (In PC97307) 2.4.3 SuperI/O Configuration 1 Register, Index 21h This register can be read or written. It is reset by hardware to 04h, 06h, 14h or 16h. See SELCS and the CFG1 strap pin in Table 2-2 on page 25. FIGURE 2-3. SuperI/O Configuration 1 Register Bit- map 76543210 Reset Required 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 SID (In PC97307) Index 20h Register, Chip ID ZWS Enable General Purpose Scratch Bits 76543210 Reset Required 0 x 1 0 x 0 0 0 SuperI/O Configuration 1 Index 21h Register, PC-AT or PS/2 Drive Mode Select CSOUT or CS0 Select Reserved Lock Scratch Bit X-Bus Data Buffer (XDB) Select |
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