PC97307 datasheet(40/218 Pages) NSC

40 / 218 page

Configuration

www.national.com

2.10.5

CS1 Base Address MSB Register, Second

Level Index 04h

This read/write register is reset by hardware to 00h. Same

as Plug and Play ISA base address register at index 60h.

See Table 2-7 on page 28.

2.10.6

CS1 Base Address LSB Register, Second Level

Index 05h

This read/write register is reset by hardware to 00h. Same

as Plug and Play ISA base address register at index 61h.

See Table 2-7 on page 28.

2.10.7

CS1 Configuration Register, Second Level

Index 06h

This read/write register is reset by hardware to 00h. It func-

tions like the CS0 Configuration Register described in Sec-

tion 2.10.3.

FIGURE 2-15. CS1 Conﬁguration Register Bitmap

2.10.8

Reserved, Second Level Index 07h

Attempts to access this register produce undefined results.

2.10.9

CS2 Base Address MSB Register, Second

Level Index 08h

This read/write register is reset by hardware to 00h. It func-

tions like the Plug and Play ISA base address register at in-

dex 60h. See Table 2-7 on page 28.

2.10.10 CS2 Base Address LSB Register, Second Level

Index 09h

This read/write register is reset by hardware to 00h. It func-

tions like the Plug and Play ISA base address register at in-

dex 61h. See Table 2-7 on page 28.

Mask Address Pins A11-A0

76543210

Reset

Required

Second Level

Mask Address Pin A3

CS1 Configuration

Mask Address Pin A1

Mask Address Pin A2

Assert Chip Select Signal on Read

Mask Address Pin A0

Unaffected by RD/WR

Assert Chip Select Signal on Write

Index 06h

2.10.11 CS2 Configuration Register, Second Level

Index 0Ah

This read/write register is reset by hardware to 00h. It func-

tions like the CS0 Configuration register.

FIGURE 2-16. CS2 Conﬁguration Register Bitmap

2.10.12 Reserved, Second Level Indexes 0Bh-0Fh

Attempts to access these registers produce undefined re-

sults.

2.10.13 Not Accessible, Second Level Indexes 10h-FFh

Not accessible because bits 7-4 of the Index register are 0.

Mask Address Pins A11-A0

76543210

Reset

Required

Second Level

Mask Address Pin A3

CS2 Configuration

Mask Address Pin A1

Mask Address Pin A2

Assert Chip Select Signal on Read

Mask Address Pin A0

Unaffected by RD/WR

Assert Chip Select Signal on Write

Index 0Ah

PC97307 датащи(PDF) 40 Page - National Semiconductor (TI)

PC97307 датащи(HTML) 40 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL