PC97307 datasheet(143/218 Pages) NSC

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UART1 and UART2 (with IR) (Logical Devices 5 and 6)

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Bit 5 - Transmitter Empty Interrupt Enable (TXEMP_IE)

Setting this bit enables interrupt generation if the trans-

mitter and TX_FIFO become empty.

0 - Disable Transmitter Empty interrupts (Default)

1 - Enable Transmitter Empty interrupts.

Bits 7,6 - Reserved

Reserved.

Interrupt Enable Register (IER), Consumer-IR Mode,

Bank 0, Offset 01h

Figure 7-7 shows the bitmap of the Interrupt Enable Regis-

ter (IER) in this mode.

FIGURE 7-7. IER Register Bitmap, Consumer-IR Mode

Bit 1-0 -

Same as in the Extended Modes of UART and Sharp-IR

(See previous sections).

Bit 2 - Link Status Interrupt Enable (LS_IE) or TX_FIFO

Underrun Interrupt Enable (TXUR_IE)

On reception, Setting this bit enables Link Status Inter-

rupts.

On transmission, Setting this bit enables TX_FIFO un-

derrun interrupts.

0 - Disable Link Status and TX_FIFO underrun inter-

rupts (Default)

1 - Enable Link Status and TX_FIFO underrun interrupts.

Bit 7-3 -

Same as in the Extended Modes of UART and Sharp-IR

(See the section “Interrupt Enable Register (IER), in the

Extended Modes of UART, Sharp-IR and SIR” on page

142).

76543210

Reset

Required

Interrupt Enable

Bank 0,

LS_IE or TXUR_IE

DMA_IE

TXEMP_IE

Reserved

RXHDL_IE

TXLDL_IE

MS_IE

Offset 01h

Consumer-IR Mode

7.11.3

Event Identification Register (EIR),

Bank 0, Offset 02h

The Event Identification Register (EIR) and the FIFO Con-

trol Register (FCR) (see next register description) share the

same address. The EIR is accessed during CPU read cycles

while the FCR is accessed during CPU write cycles.The

Event Identification Register (EIR) indicates the interrupt

source. The function of this register changes according to the

selected mode of operation.

Event Identiﬁcation Register (EIR), Non-Extended Mode

When Extended mode is not selected (EXT_SL bit in

EXCR1 register is set to 0), this register is the same as in

the 16550.

In a Non-Extended UART mode, this module prioritizes in-

terrupts into four levels. The EIR indicates the highest level

of interrupt that is pending. The encoding of these interrupts

is shown in Table 7-3.

When the EIR is being read, the display of the highest pri-

ority pending interrupt is frozen; new interrupt requests are

recorded, but the indication is not updated until the access

is complete.

FIGURE 7-8. EIR Register Bitmap, Non-Extended Modes

Bit 0 - Interrupt Pending Flag (IPF)

0 - There is an interrupt pending.

1 - No interrupt pending. (Default)

Bits 2,1 - Interrupt Priority 1,0 (IPR1,0)

When bit 0 (IPF) is 0, these bits indicate the pending in-

terrupt with the highest priority. See Table 7-3.

Default value is 00.

Bit 3 - RX_FIFO Time-Out (RXFT)

In the 16450 mode, this bit is always 0. In the 16550

mode (FIFOs enabled), this bit is set to 1 when an

RX_FIFO read time-out occurred and the associated in-

terrupt is currently the highest priority pending interrupt.

Bits 5,4 - Reserved

Read/Write 0.

Bit 7,6 - FIFOs Enabled (FEN1,0)

0 - No FIFO enabled. (Default)

1 - FIFOs are enabled (bit 0 of FCR is set to 1).

76543210

Reset

Required

Non-Extended Modes, Read Cycles

IPR1 - Interrupt Priority 1

Reserved

FEN0 - FIFOs Enabled

FEN1 - FIFOs Enabled

Event Identification

IPF - Interrupt Pending

IPR0 - Interrupt Priority 0

RXFT - RX_FIFO Time-Out

Bank 0,

Offset 02h

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