PC97307 datasheet(80/218 Pages) NSC

80 / 218 page

The Digital Floppy Disk Controller (FDC) (Logical Device 3)

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The Main Status Register (MSR) should be read to verify

that the interrupt is for a data transfer. The RQM and NON

DMA bits (bits 7 and 5, respectively) in the MSR are set to

1. The interrupt is cleared when the byte is transferred to or

from the Data Register (FIFO). To transfer the data in or out

of the Data register, you must use the address bits of the

FDC together and RD or WR must be active, i.e., A2-0 must

be valid. It is not enough to just assert the address bits of

the FDC. RD or WR must also be active for a read or write

transfer to be recognized.

The microprocessor should transfer the byte within the data

transfer service time (see Section 5.3.7 on page 76). If the

byte is not transferred within the time allotted, an overrun er-

ror is indicated in the result phase when the command ter-

minates at the end of the current sector.

An interrupt is also generated after the last byte is trans-

ferred. This indicates the beginning of the result phase. The

RQM and DIO bits (bits 7 and 6, respectively) in the MSR

are set to 1, and the NON DMA bit (bit 5) is cleared to 0. This

interrupt is cleared by reading the first result byte.

Interrupt Transfer Mode - FIFO Enabled

Interrupt transfer (non-DMA) mode with the FIFO enabled is

very similar to interrupt transfer mode with the FIFO dis-

abled. In this case, the appropriate IRQ signal is asserted

instead of DRQ, under the same FIFO threshold trigger con-

ditions.

The MSR should be read to verify that the interrupt is for a

data transfer. The RQM and non-DMA bits (bits 7 and 5, re-

spectively) in the MSR are set. To transfer the data in or out

of the Data register, you must use the address bits of the

FDC together and RD or WR must be active, i.e., A2-0 must

be valid. It is not enough to just assert the address bits of

the FDC. RD or WR must also be active for a read or write

transfer to be recognized.

Burst mode may be used to hold the IRQ signal active dur-

ing a burst, or burst mode may be disabled to toggle the IRQ

signal for each byte of a burst. The Main Status Register

(MSR) is always valid to the microprocessor. For example,

during a read command, after the last byte of data has been

read from the disk and placed in the FIFO, the MSR still in-

dicates that the execution phase is active, and that data

needs to be read from the Data Register (FIFO). Only after

the last byte of data has been read by the microprocessor

from the FIFO does the result phase begin.

The overrun and underrun error procedures for non-DMA

mode are the same as for DMA mode. Also, whether there

is an error or not, an interrupt is generated at the end of the

execution phase, and is cleared by reading the first result

phase byte.

Software Polling

If non-DMA mode is selected and interrupts are not suitable,

the microprocessor can poll the MSR during the execution

phase to determine when a byte is ready to be transferred.

The RQM bit (bit 7) in the MSR reflects the state of the IRQ

signal. Otherwise, the data transfer is similar to the interrupt

mode described above, whether the FIFO is enabled or dis-

abled.

5.4.3

Result Phase

During the result phase, the microprocessor reads a series

of result bytes from the Data Register (FIFO). These bytes

indicate the status of the command. They may indicate

whether the command executed properly, or may contain

some control information.

See the specific commands in “The FDC Command Set” on

page 86 or “Data Register (FIFO), Offset 05h” on page 76

for details.

These result bytes are read in the order specified for that

particular command. Some commands do not have a result

phase. Also, the number of result bytes varies with each

command. All result bytes must be read from the Data Reg-

ister (FIFO) before the next command can be issued.

As it does for command bytes, the Main Status Register

(MSR) controls the flow of result bytes, and must be polled

by the software before reading each result byte from the

Data Register (FIFO). The RQM bit (bit 7) and DIO bit (bit 6)

of the MSR must both be set before each result byte can be

read.

After the last result byte is read, the Command in Progress

bit (bit 4) of the MSR is cleared, and the controller is ready

for the next command.

For more information, see “The Result Phase Status Regis-

ters” on page 81.

5.4.4

Idle Phase

After a hardware or software reset, after the chip has recov-

ered from power-down mode or when there are no com-

mands in progress the controller is in the idle phase. The

controller waits for a command byte to be written to the Data

cleared in the MSR.

After receiving the first command (opcode) byte, the con-

troller enters the command phase. When the command is

completed the controller again enters the idle phase. The

Digital Data Separator (DDS) remains synchronized to the

reference frequency while the controller is idle. While in the

idle phase, the controller periodically enters the drive polling

phase.

5.4.5

Drive Polling Phase

National Semiconductor’s FDC supports the polling mode

of old 8-inch drives, as a means of monitoring any change

in status for each disk drive present in the system. This sup-

port provides backward compatibility with software that ex-

pects it.

In the idle phase, the controller enters a drive polling phase

every 1 msec, based on a 500 Kbps data transfer rate. In

the drive polling phase, the controller checks the status of

each of the logical drives (bits 0 through 3 of the MSR). The

internal ready line for each drive is toggled only after a hard-

ware or software reset, and an interrupt is generated for

drive 0.

At this point, the software must issue four SENSE INTER-

RUPT commands to clear the status bit for each drive, un-

less drive polling is disabled via the POLL bit in the

CONFIGURE command. See “Bit 4 - Disable Drive Polling

(POLL)” on page 88. The CONFIGURE command must be

issued within 500

µsec (worst case) of the hardware or soft-

ware reset to disable drive polling.

Even if drive polling is disabled, drive stepping and delayed

power-down occur in the drive polling phase. The controller

checks the status of each drive and, if necessary, it issues

a pulse on the STEP output signal with the DIR signal at the

appropriate logic level.

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