PC97307 datasheet(144/218 Pages) NSC

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UART1 and UART2 (with IR) (Logical Devices 5 and 6)

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TABLE 7-3. Non-Extended Mode Interrupt Priorities

EIR Bits

3 2 1 0

Interrupt Set and Reset Functions

Priority

Level

Interrupt Type

Interrupt Source

Interrupt Reset Control

0 0 0 1

None

0 1 1 0

Highest

Link Status

Parity error, framing error, data overrun

or break event

Read Link Status Register (LSR).

0 1 0 0

Second

Receiver High

Data Level

Event

Receiver Holding Register (RXD) full, or

RX_FIFO level equal to or above

threshold.

Reading the RXD or, RX_FIFO level

drops below threshold.

1 1 0 0

Second

RX_FIFO Time-

Out

At least one character is in the

RX_FIFO, and no character has been

input to or read from the RX_FIFO for 4

character times.

Reading the RXD port.

0 0 1 0

Third

Transmitter Low

Data Level

Event

Transmitter Holding Register or

TX_FIFO empty.

Reading the EIR Register if this

interrupt is currently the highest

priority pending interrupt, or writing

into the TXD port.

0 0 0 0

Fourth

Modem Status

Any transition on CTS, DSR or DCD or

a low to high transition on RI.

Reading the Modem Status Register

(MSR).

Event Identiﬁcation Register (EIR), Extended Mode

In Extended mode, each of the previously prioritized and

encoded interrupt sources is broken down into individual

bits. Each bit in this register acts as an interrupt pending

flag, and is set to 1 when the corresponding event occurred

or is pending, regardless of the IER register bit setting.

When this register is read the DMA event bit (bit 4) is

cleared if an 8237 type DMA is used. All other bits are

cleared when the corresponding interrupts are acknowl-

edged by reading the relevant register (e.g. reading MSR

clears MS_EV bit).

FIGURE 7-9. EIR Register Bitmap, Extended Mode

Bit 0 - Receiver High-Data-Level Event (RXHDL_EV)

When FIFOs are disabled, this bit is set to 1 when a

character is in the Receiver Holding Register.

76543210

Reset

Required

Extended Mode, Read Cycles

Event Identification

Bank 0,

DMA_EV

TXEMP-EV or PLD_EV

Reserved

RXHDL_EV

TXLDL_EV

MS_EV

LS_EV or TXHLT_EV

Offset 02h

When FIFOs are enabled, this bit is set to 1 when the

RX_FIFO is above threshold or an RX_FIFO time-out

has occurred.

Bit 1 - Transmitter Low-Data-Level Event (TXLDL_EV)

When FIFOs are disabled, this bit is set to 1 when the

Transmitter Holding Register is empty.

When FIFOs are enabled, this bit is set to 1 when the

TX_FIFO is below the threshold level.

Bit 2 - Link Status Event (LS_EV) or Transmitter Halted

Event (TXHLT_EV)

In the UART, Sharp-IR and SIR modes, this bit is set to

1 when a receiver error or break condition is reported.

When FIFOs are enabled, the Parity Error(PE), Frame

Error(FE) and Break(BRK) conditions are only reported

when the associated character reaches the bottom of

the RX_FIFO. An Overrun Error (OE) is reported as

soon as it occurs.

In the Consumer-IR mode, this bit indicates that a Link

Status Event (LS_EV) or a Transmitter Halted Event

(TXHLT_EV) occurred. It is set to 1 when any of the fol-

lowing conditions occurs:

— A receiver overrun.

— A transmitter underrun.

Bit 3 - Modem Status Event (MS_EV)

In UART mode this bit is set to 1 when any of the 0 to 3

bits in the MSR register is set to 1.

In any IR mode, the function of this bit depends on the

setting of the IRMSSL bit in the IRCR2 register (see Ta-

ble 7-4 and also “Bit 1 - MSR Register Function Select

in Infrared Mode (IRMSSL)” on page 158).

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