PC97307 datasheet(37/218 Pages) NSC

37 / 218 page

Configuration

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Bit 0 - TRI-STATE Control

When set, this bit causes the FDC pins to be in TRI-

STATE (except the IRQ and DMA pins) when the FDC is

inactive (disabled).

This bit is ORed with a bit of PMC1 register of logical de-

vice 8.

0 - FDC pins are not put in TRI-STATE.

1 - FDC pins are put in TRI-STATE.

Bits 4-1 - Reserved

Reserved.

Bit 5 - DENSEL Polarity Control

0 - DENSEL is active low for 500 Kbps or 1 Mbps data

rates.

1 - DENSEL is active high for 500 Kbps or 1 Mbps data

rates. (Default)

Bit 6 - TDR Register Mode

0 - AT Compatible TDR mode (bits 7 through 2 of TDR

are not driven).

1 - Enhanced TDR mode (bits 7 through 2 of TDR are

driven on TDR read).

Bit 7 - Four Drive Encode

0 - Two ﬂoppy drives are directly controlled by DR1-0,

MTR1-0.

1 - Four ﬂoppy drives are controlled with the aid of an

external decoder.

2.6.2

Drive ID Register, Index F1h

This read/write register is reset by hardware to 00h. These

bits control bits 5 and 4 of the enhanced TDR register.

FIGURE 2-10. Drive ID Register Bitmap

Bits 1,0 - Drive 0 ID

These bits are reflected on bits 5 and 4, respectively, of

the Tape Drive Register (TDR) of the FDC when drive 0

is accessed. See Section 5.3.4 on page 73.

Bits 3,2 - Drive 1 ID

These bits are reflected on bits 5 and 4, respectively, of

the TDR register of the FDC when drive 1 is accessed.

See Section 5.3.4 on page 73.

Bits 7-4 - Reserved

These bits are reserved.

Drive 0 ID

Reserved

76543210

Reset

Required

Index F1h

Drive ID Register,

Drive 1 ID

2.7

PARALLEL PORT CONFIGURATION REGISTER

(LOGICAL DEVICE 4)

2.7.1

SuperI/O Parallel Port Configuration Register,

Index F0h

This read/write register is reset by hardware to F2h. For nor-

mal operation and to maintain compatibility with future

chips, do not change bits 7 through 4.

FIGURE 2-11. SuperI/O Parallel Port Conﬁguration

Bit 0 - TRI-STATE Control

When set, this bit causes the parallel port pins to be in

TRI-STATE (except IRQ and DMA pins) when the paral-

lel port is inactive (disabled). This bit is ORed with a bit

of the PMC1 register of logical device 8.

Bit 1 - Clock Enable

0 - Parallel port clock disabled.

ECP modes and EPP time-out are not functional

when the logical device is active. Registers are

maintained.

1 - Parallel port clock enabled.

All operation modes are functional when the logical

device is active. This bit is ANDed with a bit of the

PMC3 register of the power management device

(logical device 8).

Bit 2 - Reserved

This bit is reserved.

Bit 3 - Reported Parallel Port of PnP ISA Resource Data

Report to the ISA PnP Resource Data the device identi-

fication.

0 - ECP device.

1 - SPP device.

Bit 4 - Conﬁguration Bits within the Parallel Port

0 - The registers at base (address) + 403h, base +

404h and base + 405h are not accessible (reads

and writes are ignored).

1 - When ECP is selected by bits 7 through 5, the reg-

isters at base (address) + 403h, base + 404h and

base + 405h are accessible.

TRI-STATE Control

Parallel Port Mode Select

76543210

Reset

Required

Index F0h

Configuration Register,

PP of PnP ISA Resource Data

SuperI/O Parallel Port

Clock Enable

Reserved

Configuration Bits within the Parallel Port

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