PC97307 datasheet(58/218 Pages) NSC

58 / 218 page

Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)

www.national.com

4.4

DETAILED FUNCTIONAL DESCRIPTION

4.4.1

The ONCTL Signal

The APC checks when activation or deactivation conditions

are met, and sets or resets the ONCTL signal accordingly.

This signal activates the system power supply. ONCTL is

physically generated as the output of the ONCTL (set-reset)

flip-flop. The state of ONCTL depends on the following:

• The status of the Mask ONCTL Activation (MOAP) bit

• Presence of activation conditions

• Power source condition

• The preceding state of ONCTL

The Preceding State of the ONCTL Signal

A power failure may occur when the system is active or in-

active. The ONCTL flip-flop maintains the state of the

ONCTL signal at the time of the power failure. When power

is restored, the ONCTL signal returns the system to a state

determined by the saved status of ONCTL and the saved

value of the MOAP bit.

The MOAP Bit

The Mask ONCTL Activation in Power Failure (MOAP) bit

(bit 4 of APCR1) is controlled by software. It makes it possi-

ble to choose the desired system response upon return

from a power failure, and decide whether the system re-

mains inactive until it is manually switched on, or resumes

the state that prevailed at the time of the power failure, in-

cluding enabling of “wake-up” events, as described in the

next section.

Logical Conditions that Deﬁne the Status of the ONCTL

Flip-Flop

The logical conditions described here set or reset the

ONCTL flip-flop. They reflect the physical events described

in “System Power-Up and Power-Off Activation Event De-

scription” on page 59.

Conditions that set the ONCTL flip-flop:

• Timer Enable bit is 1 and there is a match between

the real-time clock and the time speciﬁed in the pre-

determined date registers.

• Switch On event occurred.

• Timer Match Enable bit is 1 and there is a match be-

tween the real-time clock and the time speciﬁed in the

pre-determined date registers.

User software must ensure unused date/time fields are

coherent, to ensure the comparison of valid bits gives

the correct results.

• The RING enable bit (bit 3 of APCR2) is 1 and one of

the following occurs:

— Bit 2 of APCR2 is 0, and a high-to-low transition is

detected on the RING input pin.

— Bit 2 0f APCR2 is 1 and a train of pulses is detected

on the RING input pin.

• RI1,2 Enable bit(s) are 1 and a high to low transition is

detected on the RI1,2 input pin(s).

Conditions that put the ONCTL flip-flop in a 1 state (inactive

ONCTL signal):

• Switch Off Delay Enable bit is 0 and Switch Off event

occurred.

• Switch Off Delay Enable bit is 1 and Fail-safe Timer

reached terminal count.

• A 1 is written to Software Off Command bit.

4.4.2

Entering Power States

Power Up

When power is first applied to the RTC, the APC registers

are initialized to default values defined in APCR1, APCR2

and APSR. See “Bank 2 Registers, APC Memory Bank” on

page 65. This situation is defined by the appearance of

VBAT or VCCH with no previous power.

The APC powers up when the RTC supply is applied from

any source and is always in an active state. The RTC may

be powered up, but inactive; this occurs if bit 0 of the regis-

ter at index 30h (see Section 2.3 on page 26) of this logical

device is not set. In this situation, the APC registers are not

accessible, since they are only accessed via the RTC. This

is also true of the general-purpose battery-backed RAM.

FIGURE 4-10. Switch Event Detector

Debounce

Switch-On Event

Switch-Off Event

SWITCH

VDD

VCCH

Falling

Edge

Detector

VDD Exists

POR

Edge or Trigger POR Select

Level POR Clear

APCR1 Register, Bit 2

APCR1 Register, Bit 3

PC97307 датащи(PDF) 58 Page - National Semiconductor (TI)

PC97307 датащи(HTML) 58 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL