PC97307 datasheet(140/218 Pages) NSC

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UART1 and UART2 (with IR) (Logical Devices 5 and 6)

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internal flag is cleared. The internal flag is also cleared and

the transmitter starts transmitting when a time-out condition

is reached. This prevents some bytes from being in the

TX_FIFO indefinitely if the threshold is not reached.

The time-out mechanism is implemented by a timer that is

enabled when the internal flag is set and there is at least

one byte in the TX_FIFO. Whenever a byte is loaded into

the TX_FIFO the timer gets reloaded with the initial value. If

no bytes are loaded for a 64-

µsec time, the timer times out

and the internal flag is cleared, thus enabling the transmit-

ter.

7.9

AUTOMATIC FALLBACK TO A NON-EXTENDED

UART MODE

The automatic fallback feature supports existing legacy

software packages that use the 16550 UART by automati-

cally turning off any Extended mode features and switches

the UART to Non-Extended mode when either of the LB-

GD(L) or LBGD(H) ports in bank 1 is read from or written to

by the CPU.

This eliminates the need for user intervention prior to run-

ning a legacy program.

In order to avoid spurious fallbacks, alternate baud rate reg-

isters are provided in bank 2. Any program designed to take

advantage of the UART’s extended features, should not use

LBGD(L) and LBGD(H) to change the baud rate. It should

use the BGD(L) and BGD(H) registers instead. Access to

these ports will not cause fallback.

Fallback can occur in any mode. In Extended UART mode,

fallback is always enabled. In this case, when a fallback oc-

curs, the following happens:

• Transmission and Reception FIFOs switch to 16 levels.

• A value of 13 is selected for the baud generator pres-

caler

• The BTEST and ETDLBK bits in the EXCR1 register

are cleared.

• UART mode is selected.

• A switch to a Non-Extended UART mode occurs.

When a fallback occurs in a Non-Extended UART mode, the

last two of the above actions do not take place.

No switch to UART mode occurs if either SIR or Sharp-IR

mode was selected. This prevents spurious switching to

UART mode when a legacy program running in infrared

mode accesses the baud generator divisor registers from

bank 1.

Fallback from a Non-Extended mode can be disabled by

setting the LOCK bit in register EXCR2. When LOCK is set

to 1 and the UART is in a Non-Extended mode, two scratch

registers overlaid with LBGD(L) and LBGD(H) are enabled.

Any attempted CPU access of LBGD(L) and LBGD(H) ac-

cesses the scratch registers, and the baud rate setting is not

affected. This feature allows existing legacy programs to

run faster than 115.2 Kbps.

7.10 OPTICAL TRANSCEIVER INTERFACE

This module implements a flexible interface for the external

infrared transceiver. Several signals are provided for this

purpose. A transceiver module with one or two reception

signals, or two transceiver modules can interface directly

with this module without any additional logic.

Since various operational modes are supported by this

module, the transmitter power as well as the receiver filter

in the transceiver module must be configured according to

the selected mode.

This module provides four interface pins to control the infra-

red transceiver. ID/IRSL(2-0) are three I/O pins and ID3 is

an Input pin. All of these pins are powered up as inputs.

When in input mode, they can be used to read the identifi-

cation data of Plug-n-Play infrared adapters.

When in output mode, the logic levels of IRSL(2-0) can be

either controlled directly by the software by setting bits 2-0

of the IRCFG1 register, or they can be automatically select-

ed by this module whenever the operation mode changes.

The automatic transceiver configuration is enabled by set-

ting the AMCFG bit (bit 7) in the IRCFG4 register to 1. It al-

lows the low-level functional details of the transceiver

module being used to be hidden from the software drivers.

The operation mode settings for the automatic configuration

are determined by various bit fields in the Infrared Interface

Configuration registers (IRCFG[4-1]) that must be pro-

grammed when the UART is initialized.

The ID0/IRSL0/IRRX2 pin can also be used as an input to

support an additional infrared reception signal. In this case,

however, only two configuration pins are available.

The IRSL0_DS and IRSL21_DS bits in the IRCFG4 register

determines the direction of IRSL(2-0).

7.11 BANK 0 – GLOBAL CONTROL AND STATUS

REGISTERS

In the Non-Extended modes of operation, bank 0 is compat-

ible with both the 16450 and the 16550. Upon reset, this

module defaults to the 16450 mode. In the Extended mode,

all the Registers (except RXD/ TXD) offer additional fea-

tures.

TABLE 7-2. Bank 0 Serial Controller Base Registers

Offset

Name

Description

00h

RXD/

TXD

Receiver Data Port/ Transmitter Data

Port

01h

IER

Interrupt Enable Register

02h

EIR/

FCR

Event Identiﬁcation Register/

FIFO Control Register

03h

LCR/

BSR

Link Control Register/

Bank Select Register

04h

MCR

Modem Control Register

05h

LSR

Link Status Register

06h

MSR

Modem Status Register

07h

SCR/

ASCR

Scratch Register/

Auxiliary Status and Control Register

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