PC87413 datasheet(165/257 Pages) NSC

165 / 257 page

9.0 System Wake-Up Control (SWC) (Continued)

Revision 1.2

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Special Key Sequence mode also enables detection of a specific single keystroke. To program the Keyboard/Mouse Wake-

up Detector to wake-up on a single keystroke, perform the following sequence:

1. Set KBDMODE bit in the KBDWKCTL register to ‘0’ (see Section 9.3.16 on page 193).

2. Set KBEVCFG field in the PS2CTL register to 0001b.

3. Program the PS2KEY0 and PS2KEY1 registers to 00h. This forces the detector to ignore the values of incoming data,

thus causing it to detect a keyboard event on the single keystroke.

Power Management Mode. In Power Management Key mode, the PS2KEY0 to PS2KEY7 register bank is divided into three

groups of registers: PS2KEY0 to PS2KEY2, PS2KEY3 to PS2KEY5 and PS2KEY6 to PS2KEY7. Each group can be pro-

grammed with different data bytes, allowing the bytes transmitted by the keyboard to be compared simultaneously with three

keystroke sequences. If the bytes transmitted by the keyboard (including Make and Break) are equal to the data bytes in

one register group, the related keyboard event is detected. The detection of Keyboard Event 1 (data in PS2KEY0-

PS2KEY2) sets the KBD_EVT1_STS bit, the detection of Keyboard Event 2 (data in PS2KEY3-PS2KEY5) sets the

KBD_EVT2_STS bit and the detection of Keyboard Event 3 (data in PS2KEY6-PS2KEY7) sets the KBD_EVT3_STS bit. All

three status bits are in the GPE1_STS_2 register (see Section 9.4.10 on page 210). Each status bit is cleared only when

the software writes ‘1’ to the bit. This mode enables the detection of any sequence of keys.

Note: Do not use a byte sequence that is a “subset” of the byte sequence of another (“superset”) Power Management key

event. The subset sequence has fewer bytes (set by the EVTxCFG fields in the KBDWKCTL register) than the superset se-

quence; the bytes contained in the subset sequence (as programed in the PS2KEY0 to PS2KEY7 registers) are identical to

the respective bytes of the superset sequence.

To program the Keyboard/Mouse Wake-up Detector to operate in Power Management Key mode, proceed as follows:

1. Set KBDMODE bit in the KBDWKCTL register to ‘1’ (see Section 9.3.16 on page 193).

2. Set each event configuration field (EVT1CFG, EVT2CFG and EVT3CFG) in the KBDWKCTL register to a value that in-

dicates the desired number of keystroke data bytes in the sequence, for each event. For example, to detect a sequence

of two received bytes, set EVTxCFG to 2h.

3. Program each group of the PS2KEY0-PS2KEY7 registers in sequential order with the data bytes of the keys in the se-

quence for each event.

Event Generation. Keyboard event detection from KBCLK and KBDAT is enabled (for event generation) 1 second after the

VSB power is on. This prevents the detection of false events during Keyboard VSB power-On transitions. In addition, if the

Keyboard/Mouse Power Control feature (see Section 9.2.10 on page 175) is enabled by setting the VDDFLMUX bit to ‘1’ (in

the SIOCF2 register; see Section 3.7.3 on page 50), keyboard event detection is disabled for 2 seconds from the moment

the VDD power is turned off. If this feature is disabled (VDDFLMUX = ‘0’ in SIOCF2) keyboard event detection is enabled

regardless of the VDD power status; however, the wake-up becomes effective (VDD power is turned on) only 1 second after

the VDD power was turned off.

Power Button Event

A low level signal at PWBTIN indicates that the Power button was pressed. This input, filtered by a 16 ms debouncer, is

bridged to the PWBTOUT output to synchronize an external ACPI controller (which is optional).

A detected low level signal sets the PWRBTN_STS status bit in the PM1b_STS_HIGH register (see Section 9.4.3 on

page 205) and the PWBT_EVT_STS status bit in the GPE1_STS_2 register (see Section 9.4.10 on page 210). Note, how-

ever, that the PWRBTN_STS status bit is not set if the PWRBTN_EV_DIS bit in the ACPI_CFG register is reset (see Section

9.3.32 on page 201). This functionality is required for ACPI compatibility in case the Power button event is implemented in

an (optional) external ACPI controller. Both status bits are cleared when the software writes ‘1’ to any of them. If a low level

is present at the input when software writes ‘1’ to the status bit, the status bit remains set. The low level detection from PWB-

TIN is enabled (for event generation) 1 second after the VSB power is on. This prevents the detection of false events during

VSB power-On transitions.

The Power button event is always enabled for wake-up in any sleep state. In addition, the Power button event is the only

wake-up event available after a Power Button Override or a Crowbar condition (see Section 9.2.6 on page 172).

In Legacy Power Button mode (LEGACY_PWBT = 1 in the PWONCTL register; see Section 9.3.11 on page 188), a low-

level signal at PWBTIN, when the VDD power is on, generates an S45 current sleep state (see Section 9.2.3 on page 167),

which sets ONCTL to Off. In addition, the PWRBTN_STS and the PWBT_EVT_STS status bits are reset in this situation. In

this mode, the Power button event is the only wake-up event available after ONCTL is turned off.

Sleep Button Event

A low level on SLBTIN indicates the Sleep button was pressed. This input is also filtered by a 16 ms debouncer.

A detected low level sets the SLPBTN_STS status bit in the PM1b_STS_HIGH register (see Section 9.4.3 on page 205) and

the SLBT_EVT_STS status bit in the GPE1_STS_2 register (see Section 9.4.10 on page 210). Note, however, that the

SLPBTN_STS status bit is not set if the SLPBTN_EV_DIS bit in the ACPI_CFG register is reset (see Section 9.3.32 on

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