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PC87413 датащи(PDF) 162 Page - National Semiconductor (TI) |
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PC87413 датащи(HTML) 162 Page - National Semiconductor (TI) |
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162 / 257 page ![]() 9.0 System Wake-Up Control (SWC) (Continued) www.national.com 162 Revision1.2 Figure 47. SWC Block Diagram 9.2 FUNCTIONAL DESCRIPTION 9.2.1 External Events General-Purpose Input/Output Events The PC8741x devices support 16 VSB-powered General-Purpose Input/Output events through ports GPIOE10-17 and GPIOE40-47. VDD- and VSB-powered signals can be connected to the GPIO pins to become sources of external events. A VDD-powered signal used to generate an event is internally disabled (for event generation) while VDD power is off and also for 1 second after VDD power is restored. This prevents the detection of false events during power transitions and while the signal driver is unpowered. For the same reasons, a VSB-powered signal used to generate an event is enabled only 1 second after the VSB power is on. (When VSB is off, the whole SWC module is disabled.) Each GPIOE pin has programmable polarity and an optional 16 ms debouncer (see Figure 48). The debouncer is enabled after the reset but can be disabled by software. A GPIO event can generate the system interrupts (IRQ and SMI) if the event is enabled and routed to the specific interrupt. The status, event enable and pending event routing bits to IRQ and SMI are implemented in the GPIO Ports module (see Section 7.3 on page 137). The status bit is set when an event of the programmed type (edge or level) is detected. A GPIO event can also generate the Power Management signals (the SCI interrupt, the ONCTL power supply control and the PWBTOUT signal). The status, event enable and wake-up state enable bits are implemented in the SWC module (see Figures 48 and 50). External Events IRQ SIOSMI Interrupt Routing Control SIOSCI SCI Interrupt Enable ONCTL PWBTOUT 4 Sec. Override and Power Management Signals Crowbar Enable LED1 LED2 LED Control Power Active Timers Debounce and Detection Event Status 31 Internal Events 7 24 Power Button VDD, VSB Status Current Sleep State 2 1 Hz Clock Sleep State Converter 4 2 SLP_TYPx SLP_EN SPLS3 SLPS5 SWC Watchdog 1 Min. Clock WDO Legacy Power Button S5 Power Button |
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