PC87413 datasheet(166/257 Pages) NSC

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9.0 System Wake-Up Control (SWC) (Continued)

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page 201). This functionality is required for ACPI compatibility in case the Sleep Button event is implemented in an (optional)

external ACPI controller. Both status bits are cleared when the software writes ‘1’ to either of them. If a low level is present

at the input when software writes ‘1’ to the status bit, the status bit remains set.

The low level detection from SLBTIN is enabled (for event generation) 1 second after the VSB power is on. This prevents the

detection of false events during VSB power-On transitions.

9.2.2

Internal Events

RTC Alarm Event

An RTC Alarm event is generated by the RTC functional block. An asserted RTC Alarm sets the RTC_STS status bit in the

PM1b_STS_HIGH register (see Section 9.4.3 on page 205) and the RTC_EVT_STS status bit in the GPE1_STS_3 register

(see Section 9.4.11 on page 211). Note, however, that the RTC_STS status bit is not set if the RTC_EV_DIS bit in the

ACPI_CFG register (see Section 9.3.32 on page 201) is reset. This functionality is required for ACPI compatibility in case

the RTC Alarm event is implemented in an (optional) external ACPI controller. Both status bits are cleared when the software

writes ‘1’ to any of them. If the RTC Alarm is asserted when software writes ‘1’ to the status bit, the status bit remains set.

KBC P12 Event

A KBC P12 event is detected when the P12 port of the Keyboard Controller (KBC) functional block is set to ‘1’. For this to

happen, the KBC module must be enabled (see Section 3.3.1 on page 43). Since the Keyboard Controller functional block

is powered by VDD, a P12 event can occur only when VDD is present.

A high level at the P12 port of the KBC sets the P12_EVT_STS status bit in the GPE1_STS_3 register (see Section 9.4.11

on page 211). The status bit is cleared only when the software writes ‘1’ to it. If the P12 port is at high level when software

writes ‘1’ to the status bit, the status bit remains set.

Keyboard and Mouse IRQ Events

Keyboard and Mouse IRQ events are detected when either the Keyboard IRQ or Mouse IRQ is asserted.

To enable the IRQ of a logical device to generate an IRQ event, the associated Enable bit (bit 4 of the configuration register

at index 70h; see Section 3.2.3 on page 40) must be set to ‘1’. Since the Keyboard Controller (KBC) functional block is pow-

ered by VDD, a Keyboard or Mouse IRQ event can occur only when VDD is present.

An active (level-type) Keyboard IRQ event sets the KBD_IRQ_STS status bit and an active Mouse IRQ event sets the

MS_IRQ_STS status bit. Both status bits are in the GPE1_STS_3 register (see Section 9.4.11 on page 211). A status bit is

cleared only when the software writes ‘1’ to it. If the IRQ event is active when software writes ‘1’ to the status bit, the status

bit remains set.

The ROM code used for the Keyboard Controller generates active high Keyboard and Mouse interrupts, used by the SWC

module.

Module IRQ Event

A Module IRQ event is detected when one of the Legacy modules (FDC, Parallel Port, Serial Port 1 or 2) asserts its IRQ or

when an active level is detected at the XIRQ pin (PC87416 and PC87417).

To enable the IRQ of a logical device to generate an IRQ event, the associated Enable bit (bit 4 of the configuration register

at index 70h; see Section 3.2.3 on page 40) must be set to ‘1’. Since the Legacy modules are powered by VDD, they can

assert IRQ only when VDD is present.

To enable an active level at the XIRQ pin (PC87416 and PC87417) to generate an event, both the IRQEN and the PWUREN

bits in the XIRQC register (see Section 5.4.4 on page 110) must be set to ‘1’. Since the XIRQ interrupt belongs to the X-Bus

Extension functional block powered by VSB, an active level at the XIRQ pin can also generate a Module IRQ event when

VDD is off. The XIRQ detection enabled (for event generation) 1 second after the VSB power is on. This prevents the detec-

tion of false events during VSB power-On transitions.

The MOD_IRQ_STS status bit in the GPE1_STS_3 register is set by an IRQ that is asserted by one of the Legacy modules

or by an active level at the XIRQ pin (see Section 9.4.11 on page 211). The status bit is cleared only when the software

writes ‘1’ to it. If the Module IRQ event is active when software writes ‘1’ to the status bit, the status bit remains set.

Watchdog Time-Out Event

A watchdog time-out event is generated by the watchdog function in the SWC module (see Section 9.2.9 on page 174). An

asserted watchdog event sets the WDO_EVT_STS status bit in the GPE1_STS_3 register (see Section 9.4.11 on

page 211). A status bit is cleared only when the software writes ‘1’ to it. If the watchdog event is asserted when software

writes ‘1’ to the status bit, the status bit remains set.

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