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PC87413 датащи(PDF) 239 Page - National Semiconductor (TI) |
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PC87413 датащи(HTML) 239 Page - National Semiconductor (TI) |
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239 / 257 page ![]() 11.0 Device Characteristics (Continued) Revision 1.2 239 www.national.com 11.5.2 Reset Timing VSB Power-Up Reset Figure 57. Internal VSB Power-Up Reset (No VBAT) Symbol Figure Description Reference Conditions Min1 1. Not tested. Guaranteed by design. Max1 tLRST 57 Minimum LRESET active time Power stable to end of LRESET 2048 * t32KOSC tIRST 57 Internal power-on reset time Power stable to end of internal reset 8192 * t32KOSC 2 2. Valid VBAT; the 32 KHz internal clock is running while VSB is Off (see Low Frequency Clock Timing on page 242). t32KW 3 + 8192 * t32KOSC 3. No VBAT; the 32 KHz internal clock is stopped while VSB is Off (see Low Frequency Clock Timing on page 242). tIPLV 57 Internal strap pull-down resistors, valid time4 4. Active on VSB Power-Up reset only. Before end of internal reset 512 * t32KOSC tIRST tEPLV 57 External strap pull-up resistors, valid time Before end of internal reset 512 * t32KOSC tIRST VSB (Power) 32 KHz Clock (Internal) tIRST Internal Straps tIPLV VSBONmin External Straps tEPLV t32KOSC (Internal) (Pull-Down) (Pull-Up) t32KW LRESET VSB Power-Up Reset tLRST |
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