PC87413 datasheet(197/257 Pages) NSC

197 / 257 page

9.0 System Wake-Up Control (SWC) (Continued)

Revision 1.2

197

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9.3.24

VDD Active Timer 3 Register (VDD_ON_TMR_3)

This register holds a copy of bits 24-31 of the VDD Active Timer. Whenever the VDD_ON_TMR_3 register is read, the

updating of all four VDD_ON_TMR_0 to VDD_ON_TMR_3 registers is resumed. Therefore, this register must be read

last. It is reset by hardware to 00h.

Power Well:VPP

Location: Bank 1, Offset 13h

Type:

9.3.25

VSB Active Timer 0 Register (VSB_ON_TMR_0)

This register holds a copy of bits 0-7 of the VSB Active Timer. Whenever the VSB_ON_TMR_0 register is read, the

updating of all four VSB_ON_TMR_0 to VSB_ON_TMR_3 registers is stopped, freezing the count value. Therefore, this

Power Well:VPP

Location: Bank 1, Offset 14h

Type:

9.3.26

VSB Active Timer 1 Register (VSB_ON_TMR_1)

This register holds a copy of bits 8-15 of the VSB Active Timer. It is reset by hardware to 00h.

Power Well:VPP

Location: Bank 1, Offset 15h

Type:

Bit

43210

Name

VDD Timer Data Bits 24-31

Reset

00000

Bit

Description

7-0

VDD Timer Data, bits 24-31.

Bit

43210

Name

VSB Timer Data Bits 0-7

Reset

00000

Bit

Description

7-0

VSB Timer Data, bits 0-7. An LSBit is equivalent to 1 second of the VDD power being active (On).

Bit

43210

Name

VSB Timer Data Bits 8-15

Reset

00000

Bit

Description

7-0

VSB Timer Data, bits 8-15.

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