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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PC87413 датащи(PDF) 196 Page - National Semiconductor (TI) |
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PC87413 датащи(HTML) 196 Page - National Semiconductor (TI) |
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196 / 257 page  9.0 System Wake-Up Control (SWC) (Continued) www.national.com 196 Revision1.2 9.3.21 VDD Active Timer 0 Register (VDD_ON_TMR_0) This register holds a copy of bits 0-7 of the VDD Active Timer. Whenever the VDD_ON_TMR_0 register is read, the updating of all four VDD_ON_TMR_0 to VDD_ON_TMR_3 registers is stopped, freezing the count value. Therefore, this register must be read first. It is reset by hardware to 00h. Power Well:VPP Location: Bank 1, Offset 10h Type: RO 9.3.22 VDD Active Timer 1 Register (VDD_ON_TMR_1) This register holds a copy of bits 8-15 of the VDD Active Timer. It is reset by hardware to 00h. Power Well:VPP Location: Bank 1, Offset 11h Type: RO 9.3.23 VDD Active Timer 2 Register (VDD_ON_TMR_2) This register holds a copy of bits 16-23 of the VDD Active Timer. It is reset by hardware to 00h. Power Well:VPP Location:Bank 1, Offset 12h Type: RO Bit 76 5 43210 Name VDD Timer Data Bits 0-7 Reset 0 0 0 00000 Bit Description 7-0 VDD Timer Data, bits 0-7. An LSBit is equivalent to 1 second of the VDD power being active (On). Bit 76 5 43210 Name VDD Timer Data Bits 8-15 Reset 0 0 0 00000 Bit Description 7-0 VDD Timer Data, bits 8-15. Bit 76 5 43210 Name VDD Timer Data Bits 16-23 Reset 0 0 0 00000 Bit Description 7-0 VDD Timer Data, bits 16-23. |
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