PEB2256HT datasheet(30/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Pin Descriptions

Data Sheet

2002-08-27

ALE

I + PU

Address Latch Enable

A high on this line indicates an address on an

external multiplexed address/data bus. The

address information provided on lines A(7:0) is

internally latched with the falling edge of ALE.

This function allows the FALC

®56 to be

connected to a multiplexed address/data bus

without the need for external latches. In this

case, pins A(7:0) must be connected to the

data bus pins externally. In case of

demultiplexed mode this pin can be connected

directly to

DD or can be left open.

RD/DS

I + PU

Read Enable (Intel bus mode)

This signal indicates a read operation. When

the FALC

®56 is selected via CS, the RD signal

enables the bus drivers to output data from an

internal register addressed by A(7:0) to the

Data Bus.

Data Strobe (Motorola bus mode)

This pin serves as input to control read/write

operations.

WR/RW

I + PU

WRite Enable (Intel bus mode)

This signal indicates a write operation. When

CS is active the FALC

®56 loads an internal

Read/Write Enable (Motorola bus mode)

This signal distinguishes between read and

write operation.

DBW

I + PU

Data Bus Width (Bus interface mode)

A low signal on this input selects the 8-bit bus

interface mode. A high signal on this input

selects the 16-bit bus interface mode. In this

case word transfer to/from the internal

registers is enabled. Byte transfers are

implemented by using A0 and BHE/BLE.

Table 1

Pin Definitions - Microprocessor Interface (cont’d)

No.

Ball

No.

Symbol

Input (I)

Output (O)

Supply (S)

Function

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