PEB2256HT datasheet(87/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

2002-08-27

4.2.3.7

a-Bit Access (E1)

Due to signaling procedures using the five S

a-bits (S

a4…Sa8) of every other frame of the

CRC multiframe structure, three possibilities of access by the microprocessor are

implemented.

• The standard procedure allows reading/writing the S

a-bit registers RSW, XSW without

further support. The S

a-bit information is updated every other frame.

• The advanced procedure, enabled by bit FMR1.ENSA, allows reading/writing the S

bit registers RSA4…8, XSA4…8.

A transmit or receive multiframe begin interrupt (ISR0.RMB or ISR1.XMB) is provided.

Registers RSA(8:4) contains the service word information of the previously received

CRC-multiframe or 8 doubleframes (bit slots 4 to 8 of every service word). These

registers are updated with every multiframe begin interrupt ISR0.RMB.

With the transmit multiframe begin an interrupt ISR1.XMB is generated and the contents

of the registers XSA(8:4) is copied into shadow registers. The contents is subsequently

sent out in the service words of the next outgoing CRC multiframe (or every

doubleframe) if none of the time slot 0 transparent modes is enabled. The transmit

multiframe begin interrupt XMB request that these registers issue should be serviced. If

requests for new information are ignored, the current contents is repeated.

• The extended access through the receive and transmit FIFOs of the signaling

controller. In this mode it is possible to transmit/receive a HDLC frame or a transparent

bit stream in any combination of the S

a-bits. Enabling is done by setting of bit

CCR1.EITS and the corresponding bits XC0.SA8E to SA4E/TSWM.TSA8 to TSA4

and resetting of registers TTR(4:1), RTR(4:1) and FMR1.ENSA. The access to and

from the FIFOs is supported by ISR0.RME, RPF and ISR1.XPR, ALS.

a6-Bit Detection according to ETS 300233

Four consecutive received S

a6-bits are checked for the combinations defined by

ETS

300233. The FALC56 detects the following fixed S

a6-bit combinations: SA61,

SA62, SA63, SA64 = 1000, 1010, 1100, 1110, 1111. All other possible 4-bit

combinations are grouped to status “X”.

A valid S

a6-bit combination must occur three times in a row. The corresponding status

bit in register RSA6S is set. Register RSA6S is of type “clear on read”. Any status change

of the S

a6-bit combinations causes an interrupt (ISR0.SA6SC).

During the basic frame asynchronous state update of register RSA6S and interrupt

status ISR0.SA6SC is disabled. In multiframe format the detection of the S

a6-bit

combinations can be done either synchronously or asynchronously to the submultiframe

(FMR3.SA6SY). In synchronous detection mode updating of register RSA6S is done in

the multiframe synchronous state (FRS0.LMFA = 0). In asynchronous detection mode

updating is independent of the multiframe synchronous state.

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