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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PEB2256HT датащи(PDF) 79 Page - Infineon Technologies AG |
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PEB2256HT датащи(HTML) 79 Page - Infineon Technologies AG |
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79 / 490 page  FALC56 V1.2 PEB 2256 Functional Description E1 Data Sheet 79 2002-08-27 4.2 Framer Operating Modes (E1) 4.2.1 General Bit: FMR1.PMOD = 0 PCM line bit rate : 2.048 Mbit/s Single frame length : 256 bit, No. 1…256 Framing frequency : 8 kHz HDLC controller : nx64 kbit/s, n = 1 to 32 or n ×4 kbit/s, n = 1 to 5 Organization : 32 time slots, No. 0…31 with 8 bits each, No. 1…8 The operating mode of the FALC56 is selected by programming the carrier data rate and characteristics, line code, multiframe structure, and signaling scheme. The FALC56 implements all of the standard framing structures for E1 or PCM 30 (CEPT, 2.048 Mbit/s) carriers. The internal HDLC or CAS controller supports all signaling procedures including signaling frame synchronization/synthesis and signaling alarm detection in all framing formats. The time slot assignment from the PCM line to the system highway and vice versa is performed without any changes of numbering (TS0 ↔ TS0, …, TS31 ↔ TS31). Summary of E1 Framing Modes • Doubleframe format according to ITU-T G. 704 • Multiframe format according to ITU-T G. 704 • CRC4 processing according to ITU-T G. 706 • Multiframe format with CRC4 to non CRC4 interworking according to ITU-T G. 706 • Multiframe format with modified CRC4 to non CRC4 interworking • Multiframe format with CRC4 performance monitoring After reset, the FALC56 is switched into doubleframe format automatically. Switching between the framing formats is done by programming bits FMR2.RFS1/0 and FMR3.EXTIW for the receiver and FMR1.XFS for the transmitter. |
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