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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PEB2256HT датащи(PDF) 31 Page - Infineon Technologies AG |
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PEB2256HT датащи(HTML) 31 Page - Infineon Technologies AG |
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31 / 490 page  FALC56 V1.2 PEB 2256 Pin Descriptions Data Sheet 31 2002-08-27 11 E1 IM I + PU Interface Mode The level at this pin defines the bus interface mode: A low signal on this input selects the Intel interface mode. A high signal on this input selects the Motorola interface mode. 54 D9 CS I + PU Chip Select A low signal selects the FALC ®56 for read and write operations. This allows to connect multiple devices to a single data/address bus. 55 C9 BHE/ BLE I + PU Bus High Enable (Intel bus mode) If 16-bit bus interface mode is enabled, this signal indicates a data transfer on the upper byte of the data bus D(15:8). In 8-bit bus interface mode this signal has no function and should be tied to V DD or left open. Bus Low Enable (Motorola bus mode) If 16-bit bus interface mode is enabled, this signal indicates a data transfer on the lower byte of the data bus D(7:0). In 8-bit bus interface mode this signal has no function and should be tied to V DD or left open. 57 C7 INT O/oD INTerrupt Request INT serves as general interrupt request for all interrupt sources. These interrupt sources can be masked via registers IMR(5:0). Interrupt status is reported via registers GIS (Global Interrupt Status) and ISR(5:0). Output characteristics (push-pull active low/ high, open drain) are determined by programming register IPC. (oD = open drain output) Table 1 Pin Definitions - Microprocessor Interface (cont’d) Pin No. Ball No. Symbol Input (I) Output (O) Supply (S) Function |
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