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PEB2256HT датащи(PDF) 46 Page - Infineon Technologies AG

номер детали PEB2256HT
подробное описание детали  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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производитель  INFINEON [Infineon Technologies AG]
домашняя страница  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT датащи(HTML) 46 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
Pin Descriptions
Data Sheet
46
2002-08-27
60
61
62
63
B8
A9
A8
B7
XPA
XPB
XPC
XPD
I + PU
Transmit Clock (TCLK)
PC(1:4).XPC(3:0) = 0011
A 2.048/8.192-MHz (E1) or 1.544/6.176-MHz
(T1/J1) clock has to be sourced by the system
if the internally generated transmit clock
(generated by DCO-X) shall not be used.
Optionally this input is used as a
synchronization clock for the DCO-X circuitry
with a frequency of 2.048 (E1) or 1.544 MHz
(T1/J1).
O
Transmit Multiframe Begin (XMFB)
PC(1:4).XPC(3:0) = 0100
XMFB marks the beginning of every
transmitted multiframe on XDI. The signal is
active high for one 2.048 (E1) or 1.544 MHz
(T1/J1) period.
O
Transmit Signaling Marker (XSIGM)
PC(1:4).XPC(3:0) = 0101
E1: Marks the transmit time slots on XDI of
every frame which are defined by register
TTR(1:4).
T1/J1: Marks the transmit time slots on XDI of
every frame which are defined by register
TTR(1:4) (if not CAS-BR is used).
When using the CAS-BR signaling scheme the
robbed bit of each channel in every sixth frame
is marked.
Table 4
Pin Definitions - System Interface (cont’d)
Pin
No.
Ball
No.
Symbol
Input (I)
Output (O)
Supply (S)
Function



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