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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PEB2256HT датащи(PDF) 60 Page - Infineon Technologies AG |
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PEB2256HT датащи(HTML) 60 Page - Infineon Technologies AG |
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60 / 490 page  FALC56 V1.2 PEB 2256 Functional Description E1 Data Sheet 60 2002-08-27 4 Functional Description E1 4.1 Receive Path in E1 Mode Figure 13 Receive Clock System (E1) 4.1.1 Receive Line Interface For data input, three different data types are supported: • Ternary coded signals received at multifunction ports RL1 and RL2 from a -10 dB (short-haul, LIM0.EQON = 0) or -43 dB (long-haul, LIM0.EQON = 1) ternary interface. The ternary interface is selected if LIM1.DRS is reset. • Digital dual-rail signals received on ports RDIP and RDIN. The dual-rail interface is selected if LIM1.DRS and FMR0.RC1 is set. • Unipolar data on port ROID received from a fiber-optical interface. The optical interface is selected if LIM1.DRS is set and FMR0.RC1 is reset. 4.1.2 Receive Short and Long-Haul Interface The FALC56 has an integrated short-haul and long-haul line interface, including a receive equalization network and noise filtering. Equalizer Clock & Data Recovery DPLL Line Decoder Alarm Detector Analog LOS Detector RDATA RCLK SYNC RL1/RDIP/ROID RL2/RDIN/RCLKI DCO-R Receive Jitter Attenuator MCLK FSC Receive System Interface F0117 |
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