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PEB2256HT датащи(PDF) 71 Page - Infineon Technologies AG |
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PEB2256HT датащи(HTML) 71 Page - Infineon Technologies AG |
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71 / 490 page ![]() FALC56 V1.2 PEB 2256 Functional Description E1 Data Sheet 71 2002-08-27 • Frame alignment between system frame and receive route frame • Reporting and controlling of slips Controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel data which is circularly written to the elastic buffer using internally generated receive route clock (RCLK). Reading of stored data is controlled by the system clock sourced by SCLKR or by the receive jitter attenuator and the synchronization pulse (SYPR) together with the programmed offset values for the receive time slot/clock slot counters. After conversion into a serial data stream, the data is given out on port RDO. If the receive buffer is bypassed programming of the time slot offset is disabled and data is clocked off with RCLK instead of SCLKR. In one frame or short buffer mode the delay through the receive buffer is reduced to an average delay of 128 or 46 bits. In bypass mode the time slot assigner is disabled. In this case SYPR programmed as input is ignored. Slips are performed in all buffer modes except the bypass mode. After a slip is detected the read pointer is adjusted to one half of the current buffer size. The following table gives an overview of the receive buffer operating mode. I In single frame mode (SIC1.RBS), values of receive time slot offset (RC1/0) have to be specified great enough to prevent too great approach of frame begin of line side and frame begin of system side. Figure 19 gives an idea of operation of the receive elastic buffer: A slip condition is detected when the write pointer (W) and the read pointer (R) of the memory are nearly coincident, i.e. the read pointer is within the slip limits (S +, S –). If a Table 15 Receive Buffer Operating Modes (E1) Buffer Size (SIC1.RBS1/0) TS Offset programming (RC1/0) + SYPR = input Slip performance bypass 1) 1) In bypass mode the clock provided on pin SCLKR is ignored. Clocking is done with RCLK. disabled recommended: SYPR = output no short buffer not recommended, recommended: SYPR = output yes 1 frame not recommended, recommended: SYPR = output yes 2 frames enabled yes |
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