PEB2256HT datasheet(92/490 Pages) INFINEON

92 / 490 page

FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

2002-08-27

loss of CAS multiframe alignment or a receive slip occurs. The internal signaling buffer

RS(16:1) is frozen. Optionally automatic freeze signaling is disabled by setting bit

SIC3.DAF.

4.3.3

Error Counter

The FALC56 offers six error counters where each of them has a length of 16 bit. They

record code violations, framing bit errors, CRC4-bit errors and CRC4 error events which

are flagged in the different S

a6-bit combinations or the number of received multiframes

in asynchronous state or the change of frame alignment (COFA). Counting of the

multiframes in the asynchronous state and the COFA parameter is done in a 6/2 bit

counter and is shared with CEC3L/H. Each of the error counters is buffered. Buffer

updating is done in two modes:

• One-second accumulation

• On demand by handshake with writing to the DEC register

In the one-second mode an internal/external one-second timer updates these buffers

and resets the counter to accumulate the error events in the next one-second period.

The error counter cannot overflow. Error events occurring during an error counter reset

are not lost.

4.3.4

Errored Second

The FALC56 supports the error performance monitoring by detecting the following

alarms or error events in the received data:

framing errors, CRC errors, code violations, loss of frame alignment, loss-of-signal,

alarm indication signal, E-bit error, receive and transmit slips.

With a programmable interrupt mask register ESM all these alarms or error events can

generate an errored second interrupt (ISR3.ES) if enabled.

4.3.5

One-Second Timer

Additionally, a one-second timer interrupt can be generated internally to indicate that the

enabled alarm status bits or the error counters have to be checked. The one-second

timer signal is output on port SEC/FSC (GPC1.CSFP1/0). Optionally synchronization to

an external second timer is possible which has to be provided on pin SEC/FSC.

Selecting the external second timer is done with GCR.SES. Refer also to register GPC1

for input/output selection.

4.3.6

In-Band Loop Generation and Detection

The FALC56 generates and detects a framed or unframed in-band loop-up (activate) and

loop-down (deactivate) pattern with bit error rates up to 10

-2. Framed or unframed in-

band loop code is selected by LCR1.FLLB. Replacing transmit data with the in-band loop

codes is done by programming FMR3.XLD/XLU.

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