PEB2256HT datasheet(9/490 Pages) INFINEON

9 / 490 page

FALC56 V1.2

PEB 2256

List of Figures

Page

Data Sheet

2002-08-27

Figure 1

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 2

Multiple E1/T1/J1 Link over Frame Relay . . . . . . . . . . . . . . . . . . . . . . 24

Figure 3

8-Channel E1/T1/J1-Interface to the ATM Layer . . . . . . . . . . . . . . . . . 25

Figure 4

Pin Configuration P-MQFP-80-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 5

Pin Configuration P-LBGA-81-1 (bottom view) . . . . . . . . . . . . . . . . . . 27

Figure 6

Pin Configuration P-LBGA-81-1 (top view) . . . . . . . . . . . . . . . . . . . . . 28

Figure 7

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 8

FIFO Word Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 9

FIFO Word Access (Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 10

Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 11

Block Diagram of Test Access Port and Boundary Scan . . . . . . . . . . . 57

Figure 12

Flexible Master Clock Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 13

Receive Clock System (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 14

Receiver Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 15

Receive Line Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 16

Protection Switching Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 17

Jitter Attenuation Performance (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 18

Jitter Tolerance (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 19

The Receive Elastic Buffer as Circularly Organized Memory . . . . . . . 72

Figure 20

Automatic Handling of Errored Signaling Units . . . . . . . . . . . . . . . . . . 75

Figure 21

2.048 MHz Receive Signaling Highway (E1) . . . . . . . . . . . . . . . . . . . . 77

Figure 22

CRC4 Multiframe Alignment Recovery Algorithms (E1). . . . . . . . . . . . 89

Figure 23

Transmitter Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 24

Transmit Clock System (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 25

Transmit Line Monitor Configuration (E1) . . . . . . . . . . . . . . . . . . . . . . 99

Figure 26

2.048 MHz Transmit Signaling Highway (E1) . . . . . . . . . . . . . . . . . . 101

Figure 27

System Interface (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 28

Receive System Interface Clocking (E1) . . . . . . . . . . . . . . . . . . . . . . 105

Figure 29

SYPR Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . 107

Figure 30

SYPR Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . 107

Figure 31

RFM Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . . 108

Figure 32

RFM Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . . 108

Figure 33

Transmit System Interface Clocking: 2.048 MHz (E1) . . . . . . . . . . . . 109

Figure 34

Transmit System Interface Clocking: 8.192 MHz/4.096 Mbit/s (E1). . 110

Figure 35

SYPX Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . 112

Figure 36

SYPX Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . 112

Figure 37

Remote Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 38

Payload Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 39

Local Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 40

Single Channel Loop-Back (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 41

Receive Clock System (T1/J1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 42

Receiver Configuration (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

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