PEB2256HT datasheet(96/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

2002-08-27

4.4.3

Transmit Jitter Attenuator (E1)

The transmit jitter attenuator DCO-X circuitry generates a "jitter-free" transmit clock and

meets the following requirements: ITU-T I.431, G. 703, G. 736 to 739, G.823 and ETSI

TBR12/13. The DCO-X circuitry works internally with the same high frequency clock as

the receive jitter attenuator. It synchronizes either to the working clock of the transmit

backplane interface or the clock provided on pin TCLK or the receive clock RCLK

(remote loop/loop-timed). The DCO-X attenuates the incoming clock jitter starting at

2 Hz with 20 dB per decade fall-off. With the jitter attenuated clock, which is directly

depending on the phase difference of the incoming clock and the jitter attenuated clock,

data is read from the transmit elastic buffer (2 frames) or from the JATT buffer (2 frames,

remote loop). Wander with a jitter frequency below 2 Hz is passed transparently.

The DCO-X accepts gapped clocks which are used in ATM or SDH/SONET applications.

The jitter attenuated clock is output on pin XCLK or optionally on pin CLK2.

In case of missing clock on pin SCLKX the DCO-X centers automatically, if selected by

bit CMR2.DCOXC = 1.

The transmit jitter attenuator can be disabled. In that case data is read from the transmit

elastic buffer with the clock sourced on pin TCLK (2.048 or 8.192 MHz). Synchronization

between SCLKX and TCLK has to be done externally.

In the loop-timed clock configuration (LIM2.ELT) the DCO-X circuitry generates a

transmit clock which is frequency synchronized on RCLK. In this configuration the

transmit elastic buffer has to be enabled.

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