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PEB2256HT датащи(PDF) 34 Page - Infineon Technologies AG

номер детали PEB2256HT
подробное описание детали  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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производитель  INFINEON [Infineon Technologies AG]
домашняя страница  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT датащи(HTML) 34 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
Pin Descriptions
Data Sheet
34
2002-08-27
Line Interface Transmit
7
D4
XL1
O (analog)
Transmit Line 1
Analog output to the external transformer.
Selected if LIM1.DRS is cleared. After reset
this pin is in high-impedance state until bit
FMR0.XC1 is set and XPM2.XLT is cleared.
XDOP
O
Transmit Data Output Positive
This digital output for transmitted dual-rail
PCM(+) route signals can provide
- half bauded signals with 50% duty cycle
(LIM0.XFB = 0) or
- full bauded signals with 100% duty cycle
(LIM0.XFB = 1)
The data is clocked with positive transitions of
XCLK in both cases. Output polarity is selected
by bit LIM0.XDOS (after reset: active low). The
dual-rail mode is selected if LIM1.DRS and
FMR0.XC1 are set. After reset this pin is in
high-impedance state until register LIM1.DRS
is set and XPM2.XLT is cleared.
XOID
O
Transmit Optical Interface Data
Unipolar data sent to a fiber-optical interface
with 2048 kbit/s (E1) or 1544 kbit/s (T1/J1)
which is clocked on the positive transitions of
XCLK. Clocking of data in NRZ code is done
with 100% duty cycle. Data in CMI code is
shifted out with 50% or 100% duty cycle on
both transitions of XCLK according to the CMI
coding. Output polarity is selected by bit
LIM0.XDOS (after reset: data is sent active
high).
The single-rail mode is selected if LIM1.DRS is
set and FMR0.XC1 is cleared. After reset this
pin is in high-impedance state until register
LIM1.DRS is set and XPM2.XLT is cleared.
Table 2
Pin Definitions - Line Interface (cont’d)
Pin
No.
Ball
No.
Symbol
Input (I)
Output (O)
Supply (S)
Function



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