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PEB2256HT датащи(PDF) 47 Page - Infineon Technologies AG

номер детали PEB2256HT
подробное описание детали  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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производитель  INFINEON [Infineon Technologies AG]
домашняя страница  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT датащи(HTML) 47 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
Pin Descriptions
Data Sheet
47
2002-08-27
60
61
62
63
B8
A9
A8
B7
XPA
XPB
XPC
XPD
O
Data Link Bit Transmit (DLX)
PC(1:4).XPC(3:0) = 0110
E1: Marks the S
a(8:4)-bits within the data
stream on XDI. The S
a(8:4)-bit positions in time
slot 0 of every frame not containing the frame
alignment signal are selected by register
XC0.SA8E to XC0.SA4E.
T1/J1: This output provides a 4-kHz signal
which marks the DL-bit position within the data
stream on XDI (in ESF mode only).
O
Transmit Clock (XCLK)
PC(1:4).XPC(3:0) = 0111
Transmit line clock of 2.048 MHz (E1) or
1.544 MHz (T1/J1) derived from SCLKX/R,
RCLK or generated internally by DCO
circuitries.
I + PU
Transmit Line Tristate (XLT)
PC(1:4).XPC(3:0) = 1000
A high level on this port sets the transmit lines
XL1/2 or XDOP/N into tristate mode. This pin
function is logically ored with register bit
XPM2.XLT.
Table 4
Pin Definitions - System Interface (cont’d)
Pin
No.
Ball
No.
Symbol
Input (I)
Output (O)
Supply (S)
Function



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