PIC17C752-08SLASHCL datasheet(143/328 Pages) MICROCHIP

143 / 328 page

DS30289A-page 143

PIC17C7XX

15.2.1.1

ADDRESSING

Once the MSSP module has been enabled, it waits for

a START condition to occur. Following the START con-

dition, the 8-bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

The SSPSR register value is loaded into the

SSPBUF register on the falling edge of the 8th

SCL pulse.

The buffer full bit, BF is set on the falling edge of

the 8th SCL pulse.

An ACK pulse is generated.

SSP interrupt ﬂag bit, SSPIF (PIR2<7>) is set

(interrupt is generated if enabled) - on the falling

edge of the 9th SCL pulse.

In 10-bit address mode, two address bytes need to be

received by the slave. The ﬁve Most Signiﬁcant bits

(MSbs) of the ﬁrst address byte specify if this is a 10-bit

address. Bit R/W (SSPSTAT<2>) must specify a write

so the slave device will receive the second address

byte. For a 10-bit address the ﬁrst byte would equal

‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs

of the address. The sequence of events for a 10-bit

address is as follows, with steps 7- 9 for slave-transmit-

ter:

Receive ﬁrst (high) byte of Address (bits SSPIF,

BF, and bit UA (SSPSTAT<1>) are set).

Update the SSPADD register with second (low)

byte of Address (clears bit UA and releases the

SCL line).

Read the SSPBUF register (clears bit BF) and

clear ﬂag bit SSPIF.

Receive second (low) byte of Address (bits

SSPIF, BF, and UA are set).

Update the SSPADD register with the ﬁrst (high)

byte of Address. This will clear bit UA and

release the SCL line.

Read the SSPBUF register (clears bit BF) and

clear ﬂag bit SSPIF.

Receive Repeated Start condition.

Receive ﬁrst (high) byte of Address (bits SSPIF

and BF are set).

Read the SSPBUF register (clears bit BF) and

clear ﬂag bit SSPIF.

15.2.1.2

SLAVE RECEPTION

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register.

When the address byte overﬂow condition exists, then

no acknowledge (ACK) pulse is given. An overﬂow con-

dition is deﬁned as either bit BF (SSPSTAT<0>) is set

or bit SSPOV (SSPCON1<6>) is set.

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR2<7>) must be cleared in soft-

ware. The SSPSTAT register is used to determine the

status of the received byte.

Note:

Following the Repeated Start condition

(step 7) in 10-bit mode, the user only

needs to match the ﬁrst 7-bit address. The

user does not update the SSPADD for the

second half of the address.

Note:

The SSPBUF will be loaded if the SSPOV

bit is set and the BF ﬂag is cleared. If a

read of the SSPBUF was performed, but

the user did not clear the state of the

SSPOV

bit

before

the

receive

occured. The ACK is not sent and the SSP-

BUF is updated.

TABLE 15-2:

DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Transfer is Received

SSPSR

→ SSPBUF

Generate ACK

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

SSPOV

Yes

Note 1: Shaded cells show the conditions where the user software did not properly clear the overﬂow condition.

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