PIC17C752-08SLASHCL datasheet(47/328 Pages) MICROCHIP

47 / 328 page

DS30289A-page 47

PIC17C7XX

Bank 2

10h

TMR1

Timer1’s register

xxxx xxxx

uuuu uuuu

11h

TMR2

Timer2’s register

xxxx xxxx

uuuu uuuu

12h

TMR3L

Timer3’s register; low byte

xxxx xxxx

uuuu uuuu

13h

TMR3H

Timer3’s register; high byte

xxxx xxxx

uuuu uuuu

14h

PR1

Timer1’s period register

xxxx xxxx

uuuu uuuu

15h

PR2

Timer2’s period register

xxxx xxxx

uuuu uuuu

16h

PR3L/CA1L

Timer3’s period register - low byte/capture1 register; low byte

xxxx xxxx

uuuu uuuu

17h

PR3H/CA1H

Timer3’s period register - high byte/capture1 register; high byte

xxxx xxxx

uuuu uuuu

Bank 3

10h

PW1DCL

DC1

DC0

—

xx-- ----

uu-- ----

11h

PW2DCL

DC1

DC0

TM2PW2

—

xx0- ----

uu0- ----

12h

PW1DCH

DC9

DC8

DC7

DC6

DC5

DC4

DC3

DC2

xxxx xxxx

uuuu uuuu

13h

PW2DCH

DC9

DC8

DC7

DC6

DC5

DC4

DC3

DC2

xxxx xxxx

uuuu uuuu

14h

CA2L

Capture2 low byte

xxxx xxxx

uuuu uuuu

15h

CA2H

Capture2 high byte

xxxx xxxx

uuuu uuuu

16h

TCON1

CA2ED1

CA2ED0

CA1ED1

CA1ED0

T16

TMR3CS

TMR2CS

TMR1CS

0000 0000

17h

TCON2

CA2OVF CA1OVF PWM2ON

PWM1ON

CA1/PR3

TMR3ON

TMR2ON

TMR1ON

0000 0000

Bank 4:

10h

PIR2

SSPIF

BCLIF

ADIF

—

CA4IF

CA3IF

TX2IF

RC2IF

000- 0010

11h

PIE2

SSPIE

BCLIE

ADIE

—

CA4IE

CA3IE

TX2IE

RC2IE

000- 0000

12h

Unimple-

mented

—

---- ----

13h

RCSTA2

SPEN

RX9

SREN

CREN

—

FERR

OERR

RX9D

0000 -00x

0000 -00u

14h

RCREG2

Serial Port Receive Register for USART2

xxxx xxxx

uuuu uuuu

15h

TXSTA2

CSRC

TX9

TXEN

SYNC

—

TRMT

TX9D

0000 --1x

0000 --1u

16h

TXREG2

Serial Port Transmit Register for USART2

xxxx xxxx

uuuu uuuu

17h

SPBRG2

Baud Rate Generator for USART2

0000 0000

Bank 5:

10h

DDRF

Data Direction Register for PORTF

1111 1111

11h

PORTF (4)

RF7/

AN11

RF6/

AN10

RF5/

AN9

RF4/

AN8

RF3/

AN7

RF2/

AN6

RF1/

AN5

RF0/

AN4

0000 0000

12h

DDRG

Data Direction Register for PORTG

1111 1111

13h

PORTG (4)

RG7/

TX2/CK2

RG6/

RX2/DT2

RG5/

PWM3

RG4/

CAP3

RG3/

AN0

RG2/

AN1

RG1/

AN2

RG0/

AN3

xxxx 0000

uuuu 0000

14h

ADCON0

CHS3

CHS2

CHS1

CHS0

—

GO/DONE

—

ADON

0000 -0-0

15h

ADCON1

ADCS1

ADCS0

ADFM

—

PCFG3

PCFG2

PCFG1

PCFG0

000- 0000

16h

ADRESL

A/D Result Register low byte

xxxx xxxx

uuuu uuuu

17h

ADRESH

A/D Result Register high byte

xxxx xxxx

uuuu uuuu

TABLE 7-3:

SPECIAL FUNCTION REGISTERS (Cont.’d)

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

MCLR,

WDT

Legend: x = unknown, u = unchanged,- = unimplemented read as '0',q - value depends on condition.

Shaded cells are unimplemented, read as '0'.

Note1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8>

whose contents are updated from or transferred to the upper byte of the program counter.

2: The TO and PD status bits in CPUSTA are not affected by a MCLR reset.

3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.

4: This is the value that will be in the port output latch.

5: When the device is conﬁgured for microprocessor or extended microcontroller mode, the operation of this

port does not rely on these registers.

6: On any device reset, these pins are conﬁgured as inputs.

PIC17C752-08/CL датащи(PDF) 47 Page - Microchip Technology

PIC17C752-08/CL датащи(HTML) 47 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL