PIC17C752-08SLASHCL datasheet(31/328 Pages) MICROCHIP

31 / 328 page

DS30289A-page 31

PIC17C7XX

6.0

INTERRUPTS

PIC17C7XX devices have 18 sources of interrupt:

• External interrupt from the RA0/INT pin

• Change on RB7:RB0 pins

• TMR0 Overﬂow

• TMR1 Overﬂow

• TMR2 Overﬂow

• TMR3 Overﬂow

• USART1 Transmit buffer empty

• USART1 Receive buffer full

• USART2 Transmit buffer empty

• USART2 Receive buffer full

• SSP Interrupt

• SSP I2C bus collision interrupt

• A/D conversion complete

• Capture1

• Capture2

• Capture3

• Capture4

• T0CKI edge occurred

There are six registers used in the control and status of

interrupts. These are:

• CPUSTA

• INTSTA

• PIE1

• PIR1

• PIE2

• PIR2

The CPUSTA register contains the GLINTD bit. This is

the Global Interrupt Disable bit. When this bit is set, all

interrupts are disabled. This bit is part of the controller

core functionality and is described in the Section 6.4.

When an interrupt is responded to, the GLINTD bit is

automatically set to disable any further interrupts, the

return address is pushed onto the stack and the PC is

loaded with the interrupt vector address. There are four

interrupt vectors. Each vector address is for a speciﬁc

interrupt source (except the peripheral interrupts which

all vector to the same address). These sources are:

• External interrupt from the RA0/INT pin

• TMR0 Overﬂow

• T0CKI edge occurred

• Any peripheral interrupt

When program execution vectors to one of these inter-

rupt vector addresses (except for the peripheral inter-

rupts), the interrupt ﬂag bit is automatically cleared.

Vectoring to the peripheral interrupt vector address

does not automatically clear the source of the interrupt.

In the peripheral interrupt service routine, the source(s)

of the interrupt can be determined by testing the inter-

rupt ﬂag bits. The interrupt ﬂag bit(s) must be cleared

in software before re-enabling interrupts to avoid inﬁ-

nite interrupt requests.

When an interrupt condition is met, that individual inter-

rupt ﬂag bit will be set regardless of the status of its cor-

responding mask bit or the GLINTD bit.

For external interrupt events, there will be an interrupt

latency.

For two cycle instructions, the latency could

be one instruction cycle longer.

The “return from interrupt” instruction, RETFIE, can be

used to mark the end of the interrupt service routine.

When this instruction is executed, the stack is “POPed”,

and the GLINTD bit is cleared (to re-enable interrupts).

FIGURE 6-1:

INTERRUPT LOGIC

RBIF

RBIE

TMR3IF

TMR3IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

CA2IF

CA2IE

CA1IF

CA1IE

TX1IF

TX1IE

RC1IF

RC1IE

T0IF

T0IE

INTF

INTE

T0CKIF

T0CKIE

GLINTD (CPUSTA<4>)

PEIE

Wake-up (If in SLEEP mode)

or terminate long write

Interrupt to CPU

PEIF

SSPIF

SSPIE

BCLIF

BCLIE

ADIF

ADIE

CA4IF

CA4IE

CA3IF

CA3IE

TX2IF

TX2IE

RC2IF

RC2IE

INTSTA

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