PIC17C752-08SLASHCL datasheet(53/328 Pages) MICROCHIP

53 / 328 page

DS30289A-page 53

PIC17C7XX

7.4

Indirect Addressing

Indirect addressing is a mode of addressing data

memory where the data memory address in the

instruction is not ﬁxed. That is, the register that is to

be read or written can be modiﬁed by the program.

This can be useful for data tables in the data memory.

Figure 7-9 shows the operation of indirect addressing.

This depicts the moving of the value to the data mem-

ory address speciﬁed by the value of the FSR register.

Example 7-1 shows the use of indirect addressing to

clear RAM in a minimum number of instructions. A

similar concept could be used to move a deﬁned num-

ber of bytes (block) of data to the USART transmit reg-

ister (TXREG). The starting address of the block of

data to be transmitted could easily be modiﬁed by the

program.

FIGURE 7-9:

INDIRECT ADDRESSING

7.4.1

INDIRECT ADDRESSING REGISTERS

The PIC17C7XX has four registers for indirect

addressing. These registers are:

• INDF0 and FSR0

• INDF1 and FSR1

Registers INDF0 and INDF1 are not physically imple-

mented. Reading or writing to these registers acti-

vates indirect addressing, with the value in the

corresponding FSR register being the address of the

data. The FSR is an 8-bit register and allows address-

ing anywhere in the 256-byte data memory address

range. For banked memory, the bank of memory

accessed is speciﬁed by the value in the BSR.

If ﬁle INDF0 (or INDF1) itself is read indirectly via an

FSR, all '0's are read (Zero bit is set). Similarly, if

INDF0 (or INDF1) is written to indirectly, the operation

will be equivalent to a NOP, and the status bits are not

affected.

Opcode

Address

File = INDFx

FSR

Instruction

Executed

Instruction

Fetched

RAM

Opcode

File

7.4.2

INDIRECT ADDRESSING OPERATION

The indirect addressing capability has been enhanced

over that of the PIC16CXX family. There are two con-

trol bits associated with each FSR register. These two

bits conﬁgure the FSR register to:

• Auto-decrement the value (address) in the FSR

after an indirect access

• Auto-increment the value (address) in the FSR

after an indirect access

• No change to the value (address) in the FSR after

an indirect access

These control bits are located in the ALUSTA register.

The FSR1 register is controlled by the FS3:FS2 bits

and FSR0 is controlled by the FS1:FS0 bits.

When using the auto-increment or auto-decrement

features, the effect on the FSR is not reﬂected in the

ALUSTA register. For example, if the indirect address

causes the FSR to equal '0', the Z bit will not be set.

If the FSR register contains a value of 0h, an indirect

read will read 0h (Zero bit is set) while an indirect write

will be equivalent to a NOP (status bits are not

affected).

Indirect addressing allows single cycle data transfers

within the entire data space. This is possible with the

use of the MOVPF and MOVFP instructions, where either

'p' or 'f' is speciﬁed as INDF0 (or INDF1).

If the source or destination of the indirect address is in

banked memory, the location accessed will be deter-

mined by the value in the BSR.

A simple program to clear RAM from 20h - FFh is

shown in Example 7-1.

EXAMPLE 7-1:

INDIRECT ADDRESSING

MOVLW

0x20

;

MOVWF

FSR0

; FSR0 = 20h

BCF

ALUSTA, FS1

; Increment FSR

BSF

ALUSTA, FS0

; after access

BCF

ALUSTA, C

; C = 0

MOVLW

END_RAM + 1

;

CLRF

INDF0, F

; Addr(FSR) = 0

CPFSEQ FSR0

; FSR0 = END_RAM+1?

GOTO

; NO, clear next

; YES, All RAM is

; cleared

PIC17C752-08/CL датащи(PDF) 53 Page - Microchip Technology

PIC17C752-08/CL датащи(HTML) 53 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL