PIC17C752-08SLASHCL datasheet(142/328 Pages) MICROCHIP

142 / 328 page

PIC17C7XX

DS30289A-page 142

The SSPSTAT register gives the status of the data

transfer. This information includes detection of a

START or STOP bit, speciﬁes if the received byte was

data or address if the next byte is the completion of

10-bit address, and if this will be a read or write data

transfer.

The SSPBUF is the register to which transfer data is

written to or read from. The SSPSR register shifts the

data in or out of the device. In receive operations, the

SSPBUF and SSPSR create a doubled buffered

receiver. This allows reception of the next byte to begin

before reading the last byte of received data. When the

complete byte is received, it is transferred to the

SSPBUF register and ﬂag bit SSPIF is set. If another

complete byte is received before the SSPBUF register

is read, a receiver overﬂow has occurred and bit

SSPOV (SSPCON1<6>) is set and the byte in the

SSPSR is lost.

The SSPADD register holds the slave address. In 10-bit

mode, the user needs to write the high byte of the

address (1111 0 A9 A8 0). Following the high byte

address match, the low byte of the address needs to be

loaded (A7:A0).

15.2.1

SLAVE MODE

In slave mode, the SCL and SDA pins must be conﬁg-

ured as inputs. The MSSP module will override the

input state with the output data when required

(slave-transmitter).

When an address is matched or the data transfer after

an address match is received, the hardware automati-

cally will generate the acknowledge (ACK) pulse, and

then load the SSPBUF register with the received value

currently in the SSPSR register.

There are certain conditions that will cause the MSSP

module not to give this ACK pulse. These are if either

(or both):

The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

The overﬂow bit SSPOV (SSPCON1<6>) was

set before the transfer was received.

If the BF bit is set, the SSPSR register value is not

loaded into the SSPBUF, but bit SSPIF and SSPOV are

set. Table 15-2 shows what happens when a data

transfer byte is received, given the status of bits BF and

SSPOV. The shaded cells show the condition where

user software did not properly clear the overﬂow condi-

tion. Flag bit BF is cleared by reading the SSPBUF reg-

ister while bit SSPOV is cleared through software.

The SCL clock input must have a minimum high and

low time for proper operation. The high and low times

of the I2C speciﬁcation as well as the requirement of the

MSSP module is shown in timing parameter #100 and

parameter #101 of the Electrical Speciﬁcations.

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