PIC17C752-08SLASHCL datasheet(60/328 Pages) MICROCHIP

номер детали	PIC17C752-08/CL

подробное описание детали	High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D

PDF	328 Pages

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производитель	MICROCHIP [Microchip Technology]

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PIC17C7XX

DS30289A-page 60

8.2

Table Writes to External Memory

Table writes to external memory are always two-cycle

instructions. The second cycle writes the data to the

external memory location. The sequence of events for

an external memory write are the same for an internal

write.

Note:

If an interrupt is pending or occurs during

the TABLWT, the two cycle table write

completes. The

RA0/INT,

TMR0,

T0CKI interrupt ﬂag is automatically

cleared or the pending peripheral inter-

rupt is acknowledged.

8.2.2

TABLE WRITE CODE

The “i” operand of the TABLWT instruction can specify

that the value in the 16-bit TBLPTR register is auto-

matically

incremented

(for

the

write).

Example 8-1, the TBLPTR register is not automatically

incremented.

EXAMPLE 8-1:

TABLE WRITE

CLRWDT

; Clear WDT

MOVLW

HIGH (TBL_ADDR) ; Load the Table

MOVWF

TBLPTRH

;

address

MOVLW

LOW (TBL_ADDR)

;

MOVWF

TBLPTRL

;

MOVLW

HIGH (DATA)

; Load HI byte

TLWT

1, WREG

;

in TABLATH

MOVLW

LOW (DATA)

; Load LO byte

TABLWT

0,0,WREG

;

in TABLATL

;

and write to

;

program memory

;

(Ext. SRAM)

FIGURE 8-5:

TABLWT

WRITE TIMING (EXTERNAL MEMORY)

Q1 Q2 Q3 Q4

AD15:AD0

Instruction

fetched

Instruction

executed

ALE

TABLWT

INST (PC+1)

INST (PC-1)

TABLWT cycle1

TABLWT cycle2

INST (PC+2)

Data write cycle

'1'

PC+1

TBL

PC+2

Data out

INST (PC+1)

Note:

If external write, and GLINTD = '1', and Enable bit = '1', then when '1'

→ Flag bit, Do table write.

The highest pending interrupt is cleared.

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