PIC17C752-08SLASHCL datasheet(23/328 Pages) MICROCHIP

23 / 328 page

DS30289A-page 23

PIC17C7XX

5.1.4

TIME-OUT SEQUENCE

On power-up the time-out sequence is as follows: First

the internal POR signal goes high when the POR trip

point is reached. If MCLR is high, then both the OST

and PWRT timers start. In general the PWRT time-out

is longer, except with low frequency crystals/resona-

tors. The total time-out also varies based on oscillator

conﬁguration. Table 5-1 shows the times that are asso-

ciated with the oscillator conﬁguration. Figure 5-5 and

Figure 5-6 display these time-out sequences.

If the device voltage is not within electrical speciﬁcation

at the end of a time-out, the MCLR/VPP pin must be

held low until the voltage is within the device speciﬁca-

tion. The use of an external RC delay is sufﬁcient for

many of these applications.

The time-out sequence begins from the ﬁrst rising edge

of MCLR.

Table 5-3 shows the reset conditions for some special

registers, while Table 5-4 shows the initialization condi-

tions for all the registers.

TABLE 5-1:

TIME-OUT IN VARIOUS SITUATIONS

TABLE 5-2:

STATUS BITS AND THEIR SIGNIFICANCE

TABLE 5-3:

RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER

Oscillator

Conﬁguration

POR, BOR

Wake up from

SLEEP

MCLR Reset

XT, LF

Greater of: 96 ms or 1024TOSC

1024TOSC

—

EC, RC

Greater of: 96 ms or 1024TOSC

——

POR

BOR (1)

Event

Power-on Reset

MCLR Reset during SLEEP or interrupt wake-up from SLEEP

WDT Reset during normal operation

WDT Wake-up during SLEEP

MCLR Reset during normal operation

Brown-out Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

CLRWDT

instruction executed

Note 1: When BODEN is enabled, else the BOR status bit is unknown.

Event

PCH:PCL

CPUSTA (4)

OST Active

Power-on Reset

0000h

--11 1100

Yes

Brown-out Reset

0000h

--11 1110

Yes

MCLR Reset during normal operation

0000h

--11 1111

MCLR Reset during SLEEP

0000h

--11 1011

Yes (2)

WDT Reset during normal operation

0000h

--11 0111

WDT Wake-up during SLEEP (3)

0000h

--11 0011

Yes (2)

Interrupt wake-up from SLEEP

GLINTD is set

PC + 1

--11 1011

Yes (2)

GLINTD is clear

PC + 1 (1)

--10 1011

Yes (2)

Legend: u = unchanged, x = unknown, - = unimplemented read as '0'.

Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and

then executed.

2: The OST is only active (on wake-up) when the Oscillator is conﬁgured for XT or LF modes.

3: The Program Counter = 0, that is, the device branches to the reset vector. This is different from the

mid-range devices.

4: When BODEN is enabled, else the BOR status bit is unknown.

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