PIC17C752-08SLASHCL datasheet(71/328 Pages) MICROCHIP

71 / 328 page

DS30289A-page 71

PIC17C7XX

FIGURE 10-3: RA3 BLOCK DIAGRAM

Note: I/O pin has protection diodes to VSS.

Data Bus

WR_PORTA

(Q4)

RD_PORTA

(Q2)

Peripheral data in

SDA out

SSP Mode

'1'

FIGURE 10-4: RA4 AND RA5 BLOCK

DIAGRAM

Note: I/O pins have protection diodes to VDD and VSS.

Data Bus

RD_PORTA

(Q2)

Serial port output signals

Serial port input signal

OE = SPEN,SYNC,TXEN, CREN, SREN for RA4

OE = SPEN (SYNC+SYNC,CSRC) for RA5

TABLE 10-1:

PORTA FUNCTIONS

TABLE 10-2:

REGISTERS/BITS ASSOCIATED WITH PORTA

Name

Bit0

Buffer Type

Function

RA0/INT

bit0

Input or external interrupt input.

RA1/T0CKI

bit1

Input or clock input to the TMR0 timer/counter, and/or an external interrupt

input.

RA2/SS/SCL

bit2

Input/Output or slave select input for the SPI or clock input for the I2C bus.

Output is open drain type.

RA3/SDI/SDA

bit3

Input/Output or data input for the SPI or data for the I2C bus.

Output is open drain type.

RA4/RX1/DT1

bit4

Input or USART1 Asynchronous Receive or

USART1 Synchronous Data.

RA5/TX1/CK1

bit5

Input or USART1 Asynchronous Transmit or

USART1 Synchronous Clock.

RBPU

bit7

—

Control bit for PORTB weak pull-ups.

Legend: ST = Schmitt Trigger input.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

MCLR,

WDT

10h, Bank 0

PORTA (1)

RBPU

—

RA5/

TX1/CK1

RA4/

RX1/DT1

RA3/

SDI/SDA

RA2/

SS/SCL

RA1/T0CKI

RA0/INT

0-xx 11xx

0-uu 11uu

05h, Unbanked

T0STA

INTEDG

T0SE

T0CS

T0PS3

T0PS2

T0PS1

T0PS0

—

0000 000-

13h, Bank 0

RCSTA1

SPEN

RX9

SREN

CREN

—

FERR

OERR

RX9D

0000 -00x

0000 -00u

15h, Bank 0

TXSTA1

CSRC

TX9

TXEN

SYNC

—

TRMT

TX9D

0000 --1x

0000 --1u

Legend:

= unknown, u = unchanged, - = unimplemented reads as '0'. Shaded cells are not used by PORTA.

Note 1:

On any device reset, these pins are conﬁgured as inputs.

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