PIC17C752-08SLASHCL datasheet(59/328 Pages) MICROCHIP

59 / 328 page

DS30289A-page 59

PIC17C7XX

8.1

Table Writes to Internal Memory

A table write operation to internal memory causes a

long write operation. The long write is necessary for

programming the internal EPROM. Instruction execu-

tion is halted while in a long write cycle. The long write

will be terminated by any enabled interrupt. To ensure

that the EPROM location has been well programmed,

a minimum programming time is required (see speciﬁ-

cation #D114). Having only one interrupt enabled to

terminate the long write ensures that no unintentional

interrupts will prematurely terminate the long write.

The sequence of events for programming an internal

program memory location should be:

Disable all interrupt sources, except the source

to terminate EPROM program write.

Raise MCLR/VPP pin to the programming volt-

age.

Clear the WDT.

Do the table write. The interrupt will terminate

the long write.

Verify the memory location (table read).

Note 1: Programming requirements must be

met. See timing speciﬁcation in electrical

speciﬁcations for the desired device.

Violating these speciﬁcations (including

temperature) may result in EPROM loca-

tions that are not fully programmed and

may lose their state over time.

Note 2: If the VPP requirement is not met, the

table write is a 2 cycle write and the pro-

gram memory is unchanged.

8.1.1

TERMINATING LONG WRITES

An interrupt source or reset are the only events that

terminate a long write operation. Terminating the long

write from an interrupt source requires that the inter-

rupt enable and ﬂag bits are set. The GLINTD bit only

enables the vectoring to the interrupt address.

If the T0CKI, RA0/INT, or TMR0 interrupt source is

used to terminate the long write; the interrupt ﬂag, of

the highest priority enabled interrupt, will terminate the

long write and automatically be cleared.

If a peripheral interrupt source is used to terminate the

long write, the interrupt enable and ﬂag bits must be

set. The interrupt ﬂag will not be automatically cleared

upon the vectoring to the interrupt vector address.

The GLINTD bit determines whether the program will

branch to the interrupt vector when the long write is

terminated. If GLINTD is clear, the program will vec-

tor, if GLINTD is set, the program will not vector to the

interrupt address.

Note 1: If an interrupt is pending, the TABLWT is

aborted (an NOP is executed). The

highest priority pending interrupt, from

the T0CKI, RA0/INT, or TMR0 sources

that is enabled, has its ﬂag cleared.

Note 2: If the interrupt is not being used for the

program

write

timing,

the

interrupt

should be disabled. This will ensure that

the interrupt is not lost, nor will it termi-

nate the long write prematurely.

TABLE 8-1:

INTERRUPT - TABLE WRITE INTERACTION

Interrupt

Source

GLINTD

Enable

Bit

Flag

Bit

Action

RA0/INT,

TMR0,

T0CKI

Terminate long table write (to internal program memory),

branch to interrupt vector (branch clears ﬂag bit).

None

Terminate long table write, do not branch to interrupt vec-

tor (ﬂag is automatically cleared).

Peripheral

Terminate long table write, branch to interrupt vector.

None

Terminate table write, do not branch to interrupt vector

(ﬂag remains set).

PIC17C752-08/CL датащи(PDF) 59 Page - Microchip Technology

PIC17C752-08/CL датащи(HTML) 59 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL