RM0319 datasheet(150/368 Pages) STMICROELECTRONICS

150 / 368 page

Fast Ethernet port (MII0)

RM0319

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Doc ID 022640 Rev 3

[11]

Overflow Error. If set, it indicates that received frame was damaged due to

buffer overflow in MAC core.

[10]

VLAN

Van Tag. If set, it indicates that the frame pointed to by this descriptor is a

VLAN frame tagged by the MAC core.

[09]

First Descriptor. If set, this descriptor contains the first buffer of the frame.

[08]

Last Descriptor. If set, it indicates that the buffers pointed to by this

descriptor are the last buffers of the frame.

[07]

IPC

checksum

error

If set, it indicates that the 16 bit IP header checksum calculated by the MAC

core did not match the received checksum bytes.

[06]

Late Collision. If set, it indicates that late collision has occurred while

receiving the frame in half-duplex mode.

[05]

Frame type. If set, it indicates that the received frame is an Ethernet-type

frame, whereas the received frame is an IEEE802.3 frame.

[04]

RWT

Receive watchdog timeout. If set, it indicates that the receive watchdog timer

has expired while receiving the current frame and the current frame is

truncated after the watchdog timeout.

[03]

Receive Error.

[02]

Dribble Bit Error. If set, it indicates that the received frame has a non-

integer multiple of bytes (odd nibbles). Valid only in MII mode.

[01]

CRC Error.

[00]

Rx MAC

address

If set, it indicates that the Rx MAC address value (register1 to register15)

matched the DA field of the frame. If cleared, it indicates that Rx MAC

Address0 matched the DA field.

Table 49.

Receive descriptor 1 (RDES1)

Bit

Name

Description

[31]

DIC

Disable Interrupt on Completion Setting this bit will prevent the setting of the

RI bit of the Status register for the received frame that ends in the buffer

pointer to by this descriptor. This, in turn, will disable the assertion of the

interrupt to the host due to RI.

[30:29] Reserved

[28:16] RBS2

Receive Buffer 2 Size. These 13 bit field reports the size (in bytes) of the

second data buffer.

Note: The RBS2 value must be a multiple of 4/8/16 depending on the width

of the bus otherwise the resulting behaviour is undefined.

[15]

RER

Receive End of Ring When set, this bit indicates that the descriptor list

reached its final descriptor. The DMA returns to the base address of the list,

creating a descriptor ring.

[14]

RCH

Second Address Chained When set, this bit indicates that the second

address in the descriptor is the Next Descriptor address rather than the

second buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a "don't

care" value. RDES1[15] takes precedence over RDES1[14].

Table 48.

Receive descriptor 0 (RDES0) (continued)

Bit

Name

Description

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